ATR0625-DK1 ATMEL [ATMEL Corporation], ATR0625-DK1 Datasheet
ATR0625-DK1
Related parts for ATR0625-DK1
ATR0625-DK1 Summary of contents
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... Includes Power Supervisor • 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance • 4 Kbytes Battery Backup Memory 8 mm × Pin QFN56 Package • • Pb-free, RoHS-compliant, Green ® Processor Core GPS Baseband Processor SuperSense ATR0625 Preliminary Rev. 4925A–GPS–02/06 ...
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... The ATR0625 is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator, and a wide range of peripheral functions on a monolithic chip, the ATR0625 provides a highly flexible and cost-effective solution for GPS applications. ATR0625 [Preliminary] 2 ® ...
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... Figure 1-1. ATR0625 Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM DBG_EN NTRST TDI TDO TCK TMS NRESET 4925A–GPS–02/06 ATR0625 [Preliminary] ...
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... Architectural Overview 2.1 Description The ATR0625 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit memories. The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption ...
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... Pin Configuration 3.1 Pinout Figure 3-1. Pinout QFN56 (Top View) Table 3-1. ATR0625 Pinout Pin Pull Resistor Pin Name QFN56 Type (Reset Value) CLK23 37 IN DBG_EN 8 IN (2) GND IN LDOBAT_IN 21 IN LDO_EN 25 IN LDO_IN 20 IN LDO_OUT 19 OUT NRESET 41 I/O Open Drain PU NSHDN 26 OUT NSLEEP 24 OUT NTRST ...
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... Table 3-1. ATR0625 Pinout (Continued) Pin Pull Resistor Pin Name QFN56 Type (Reset Value) P14 1 I/O Configurable (PD) P15 17 I/O P16 6 I/O Configurable (PU) P17 2 I/O Configurable (PD) P18 45 I/O Configurable (PU) P19 53 I/O Configurable (PU) P20 4 I/O Configurable (PD) P21 52 I/O Configurable (PU) P22 30 I/O P23 3 I/O Configurable (PU) P24 5 I/O Configurable (PU) P25 55 I/O Configurable (PD) P26 44 I/O Configurable (PU) P27 54 I/O Configurable (PU) P29 50 I/O Configurable (PU) ...
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... Signal Description Table 3-2. ATR0625 Signal Description Module Name EBI BOOT_MODE TXD1 to TXD2 USART RXD1 to RXD2 SCK1 to SCK2 USB_DP USB USB_DM APMC RF_ON AIC EXTINT0-1 AGC AGCOUT0-1 NSLEEP NSHDN RTC XT_IN XT_OUT SCK MOSI SPI MISO NSS/NPCS0 NPCS1 to NPCS3 WD NWD_OVF PIO P0 to P31 ...
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... Table 3-2. ATR0625 Signal Description (Continued) Module Name Function TMS Test Mode Select TDI Test Data In TDO Test Data Out JTAG/ICE TCK Test Clock NTRST Test Reset Input DBG_EN Debug Enable CLK23 Clock Input CLOCK MCLK_OUT Master Clock Output RESET NRESET Reset Input ...
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... GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0625 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0) ...
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... PU) 3.3.3 Serial I/O Configuration The ATR0625 features a two-stage I/O message and protocol selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port ...
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... NMEA 57.6 UBX, NMEA UBX, NMEA, RTCM NMEA NMEA GGA, RMC, GSA, GSV GGA, RMC, GSA, GSV User, Notice, Warning, User, Notice, Warning, Error Error ATR0625 [Preliminary] USART2 UBX 57.6 UBX, NMEA, RTCM UBX NAV: SOL, SVINFO MON: EXCEPT User, Notice, Warning, Error 11 ...
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... P25) depends on the settings of GPSMODE11 and GPSMODE10 (see on page Table 3-13. Pin P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON ATR0625 [Preliminary] 12 USB Power Modes 0 USB device is bus-powered (max. current limit 100 mA) 1 USB device is self-powered (Default ROM value) 13). Pin Usage of Active Antenna Supervisor ...
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... NANTSHORT) ATR0625 [Preliminary] Comment P25/NAADET0/MISO P25/NAADET0/MISO Reserved for further use. P14/NAADET1 Do not use this setting. P14/NAADET1 (Default ROM value) Reserved for further use. P14/NAADET1 Do not use this setting. Reserved for further use. P14/NAADET1 Do not use this setting. ...
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... External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL SC PURF PUXTO +3V (see Power Supply) (see Power Supply) GND NC: Not connected ATR0625 [Preliminary] 14 SIGHI SIGLO CLK23 RF_ON NSLEEP NC NRESET see Table 3- see Table 3-15 P9 see Table 3-15 P12 - 17 ...
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... Internal pull-down resistor, leave open. P31/RXD1 Internal pull-up resistor, leave open if serial interface is not used. 4925A–GPS–02/06 ATR0625 [Preliminary] 9. Can be left open if configured as output by user “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “Setting GPSMODE0 to GPSMODE12” on page “ ...
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... Connecting an Optional Serial EEPROM The ATR0625 offers the possibility to connect an external serial EEPROM. The internal ROM firmware supports to store the configuration of the ATR0625 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected with the ATR0625. The 32-bit RISC processor of the ATR0625 accesses the external memory with SPI (Serial Peripheral Interface) ...
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... In input mode, the four GPIO-pins are 5V input tolerant. Figure Figure 4-1. 2.3V to 3.6V 4925A–GPS–02/06 4-1, Figure 4-2, and Figure 4-3 show examples of the wiring of ATR0625 power supply. External Wiring Example Using Internal LDOs and Backup Power Supply NSHDN 1 µF (X7R) 1.5V to 3.6V 1 µF (X7R 3.6V ...
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... VBAT between 1.5V and 3.6V. The backup battery connected to VBAT is only discharged if the supply connected to LDOBAT_IN is shut-down. Only after VDD18 has been supplied to ATR0625 the RTC section will be initialized properly. If only VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. ...
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... USB-VSB 5V LDO 3.3V 4925A–GPS–02/06 LDO_IN NSHDN LDO_EN LDO_OUT VDD18 1 µF (X7R) VDDIO LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 1 µF (X7R) VDDUSB ATR0625 [Preliminary] ATR0625 internal LDO18 ldoin ldoen ldoout Core 1.8V to 3.3V variable IO Domain LDOBAT ldobat_in vbat vbat18 vdd RTC Backup Memory USB SM and Transceiver 19 ...
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... VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT P0, P15, P30, SIGHI, SIGLO, CLK23, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP P1, P2, P8, P9, P12 to P14, P16 to P27, P29, P31 ATR0625 internal RTC Min. Max. Unit –40 +85 °C –60 +150 °C –0.3 +1.95 V – ...
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... VDDIO = 3.0V OH P9, P13, P22 P31 P9, P13, P22 – P31 I = 1.5 mA, OL VDD_USB = 3.0V to 3.6V, DP, DM 27Ω external series resistor I = –1.5 mA, OH VDD_USB = 3.0V to 3.6V, DP, DM 27Ω external series resistor ATR0625 [Preliminary] Symbol Min. Typ. Max. VDD18 1.65 1.8 1.95 VDDIO 1.65 1.8/3.3 3.6 VDDUSB 3.0 3.3 3.6 VBAT18 1.65 1.8 3 VDD18 ...
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... VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating the USB interface. Otherwise VDD_USB may be connected to ground 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT ATR0625 [Preliminary] 22 Test Conditions Pin VDD18 = 1 ...
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... All channels disabled Note: 1. Specified value only 9. ESD Sensitivity The ATR0625 is an ESD sensitive device. The current ESD values are to be defined. Observe precautions for handling 10. LDO18 The LDO18 is a built in low dropout voltage regulator which can be used if the host system does not provide the core voltage VDD18 ...
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... Supply voltage VBAT Output Voltage (VBAT18) If switch connects to LDOBAT_IN. Output Current (VBAT18) Current consumption LDOBAT_IN Current consumption VBAT Current consumption Note: ATR0625 [Preliminary] 24 Electrical Characteristics of LDOBAT Conditions After startup (sleep/backup mode), at (1) room temperature After startup (backup mode and LDOBAT_IN = 0V), at room ...
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... Ordering Information Extended Type Number ATR0625-PYQW ATR0625-EK1 ATR0625-DK1 13. Package QFN56 Package: QFN56 Exposed pad 6.5 x 6.5 Dimensions in mm Not indicated tolerances ±0. Drawing-No.: 6.543-5121.01-4 Issue: 1; 02.09.05 4925A–GPS–02/06 Package MPQ QFN56 2000 - 0.9 max. +0 0.05 -0.05 ATR0625 [Preliminary] Remarks 8 mm × 8 mm, 0.50 mm pitch, Pb-free, ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...