ATR0622-DK1 ATMEL [ATMEL Corporation], ATR0622-DK1 Datasheet

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ATR0622-DK1

Manufacturer Part Number
ATR0622-DK1
Description
GPS Baseband Processor
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Features
16 Channel GPS Correlator
Utilizes the ARM7TDMI
128 Kbyte Internal RAM
384 Kbyte Internal ROM, Firmware Version V5.0
Position Technology Provided by u-blox
Fully Programmable External Bus Interface (EBI)
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
32 User-programmable I/O Lines
1 USB Device Port
2 USARTs
Master/Slave SPI Interface
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Core Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
4 Kbytes Battery Backup Memory
9 mm
RoHS-compliant
– 8192 Search Bins with GPS Acquisition Accelerator
– Accuracy: 2.5m CEP (Stand-Alone, S/A off)
– Time to First Fix: 34s (Cold Start)
– Acquisition Sensitivity: –140 dBm
– Tracking Sensitivity: –150 dBm
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– EmbeddedICE
– Maximum External Address Space of 8 Mbytes
– Up to 4 Chip Selects
– Software Programmable 8-bit/16-bit External Data Bus
– 2 External Interrupts
– Universal Serial Bus (USB) V2.0 Full-speed Device
– Embedded USB V2.0 Full-speed Transceiver
– Suspend/Resume Logic
– Ping-pong Mode for Isochronous and Bulk Endpoints
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8-bit to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
– Peripherals Can Be Deactivated Individually
– Geared Master Clock to Reduce Power Consumption
– Sleep State with Disabled Master Clock
– Hibernate State with 32.768 kHz Master Clock
9 mm 100-pin BGA Package (LFBGA100)
(In-circuit Emulator)
®
ARM
®
Thumb
®
Processor Core
GPS Baseband
Processor
ATR0621P1
Automotive
Summary
NOTE: This is a summary document.
The complete document is available.
For more information, please contact
your local Atmel sales office.
4975BS–GPS–05/08

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ATR0622-DK1 Summary of contents

Page 1

Features • 16 Channel GPS Correlator – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (Stand-Alone, S/A off) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –140 dBm – Tracking Sensitivity: –150 dBm ® ...

Page 2

Description The GPS baseband processor ATR0621P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consump- tion. In addition, a large number of ...

Page 3

Figure 1-1. Block Diagram NSHDN NSLEEP XT_IN XT_OUT RF_ON CLK23 P15/ANTON P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 EM_A19 EM_A1 ...

Page 4

Architectural Overview 2.1 Description The ATR0621P1 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter- faces the processor with the on-chip 32-bit ...

Page 5

Pin Configuration 3.1 Pinout Figure 3-1. Pinout LFBGA100 (Top View) Table 3-1. ATR0621P1 Pinout Pin Name LFBGA100 Pin Type CLK23 G9 IN DBG_EN H4 IN EM_A1 A6 OUT EM_A2 A5 OUT EM_A3 A4 OUT EM_A4 A2 OUT EM_A5 A3 ...

Page 6

Table 3-1. ATR0621P1 Pinout (Continued) Pin Name LFBGA100 Pin Type EM_A16 C6 OUT EM_A17 F8 OUT EM_A18 B3 OUT EM_A19 C5 OUT EM_DA0 B6 I/O EM_DA1 B10 I/O EM_DA2 C7 I/O EM_DA3 C10 I/O EM_DA4 D10 I/O EM_DA5 E7 I/O ...

Page 7

Table 3-1. ATR0621P1 Pinout (Continued) Pin Name LFBGA100 Pin Type I/O P10 E4 I/O P11 H10 I/O ...

Page 8

Table 3-1. ATR0621P1 Pinout (Continued) Pin Name LFBGA100 Pin Type TDI J2 IN TDO K3 OUT TMS J1 IN USB_DM F10 I/O USB_DP D3 I/O VBAT J7 IN (2) VBAT18 G6 OUT VDD18 E6 IN VDD18 F7 IN VDD18 F6 ...

Page 9

Signal Description Table 3-2. ATR0621P1 Signal Description Module Name EM_A0 to EM_A21 EM_DA0 to EM_DA15 External memory data bus NCS0 to NCS1 NCS2 to NCS3 NWR0 NWR1 EBI NRD NWE NOE NUB NLB BOOT_MODE TXD1-2 USART RXD1-2 SCK1-2 USB_DP ...

Page 10

Table 3-2. ATR0621P1 Signal Description (Continued) Module Name SIGHI0 SIGLO0 GPS SIGHI1 SIGLO1 TIMEPULSE GPSMODE0-12 STATUSLED NEEPROM CONFIG ANTON NANTSHORT NAADET0-1 TMS TDI TDO JTAG/ICE TCK NTRST DBG_EN CLK23 CLOCK MCLK_OUT RESET NRESET VDD18 VDDIO POWER VDD_USB GND LDOBAT_IN LDOBAT ...

Page 11

External Connections for a Working GPS System Figure 3-2. Example of an External Connection ATR0601 SIGH SIGL SC PuRF PuXTO +3V (see Power Supply) (see Power Supply) GND NC: Not connected 4975BS–GPS–05/08 ATR0621P1 SIGHI SIGLO CLK23 RF_ON NSLEEP NC ...

Page 12

... Ordering Information Extended Type Number Package ATR0621P1-7FQY LFBGA100 ATR0621P1-7FHW LFBGA100 ATR0622-EK1 ATR0622-DK1 5. Package LFBGA100 Package: R-LFBGA 100_G Dimensions Corner Top View technical drawings according to DIN specifications Drawing-No.: 6.580-5003.01-4 Issue: 2; 27.10.05 Moisture sensitivity level (MSL ...

Page 13

Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. 4975BS-GPS-05/08 4975BS–GPS–05/08 History Table 3-1 “ATR0621P1 Pinout” on page 5: Pin type ...

Page 14

Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...

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