HB28B064MM2 RENESAS [Renesas Technology Corp], HB28B064MM2 Datasheet
HB28B064MM2
Related parts for HB28B064MM2
HB28B064MM2 Summary of contents
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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... HB28B064MM2/HB28B128MM2 16 MByte/32 MByte/64 MByte/128 MByte Description These Hitachi MultiMediaCards, HB28H016MM2, HB28D032MM2, HB28B064MM2 and HB28B128MM2, are highly integrated flash memories with serial and random access capability accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface allows several cards to be stacked by through connecting their peripheral contacts ...
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HB28H016/D032/B064/B128MM2 Features • 16 MByte/32 MByte/64 MByte/128 MByte memory capacity • On card error correction • MultiMediaCard system standard compatibility System specification version 3.1 compliant SPI mode supports the single and multiple block read and write operations. ...
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Block Diagram V PP Generator Flash control All units in these Hitachi MultiMediaCards are clocked by an internal clock generator. The Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal. The ...
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HB28H016/D032/B064/B128MM2 Interface These Hitachi MultiMediaCards' interface can operate in two different modes: • MultiMediaCard mode • SPI mode Both modes are using the same pins. The default mode is the MultiMediaCard mode. The SPI mode is selected by activating (= ...
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MultiMediaCard Mode Pad Definition Pin No. Name 1 RSV 2 CMD 3 V SS1 CLK 6 V SS2 7 DAT Note power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection ...
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HB28H016/D032/B064/B128MM2 available on the market. As any other SPI device the MultiMediaCard SPI interface consists of the following four signals: CS: Host to card Chip Select signal. CLK: Host to card clock signal Data in: Host to card data signal. ...
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SPI Interface Pin Configuration MuitiMediaCard 1 Pin No. Name Type* 1 RSV NC 2 CMD I/O/PP/ SS1 CLK SS2 7 DAT I/O/PP Note power supply; I: ...
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HB28H016/D032/B064/B128MM2 MultiMediaCard Registers in SPI Mode Name Available in SPI mode Width (Bytes) OCR Yes CID Yes RCA No CSD Yes Rev.5.0, Jan. 2003, page Description 4 Operation condition register. 16 Card identification data (serial number, manufacturer ...
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Operation Condition Register (OCR) This register indicates supported voltage range of these Hitachi MultiMediaCards bit wide register and for read only. OCR Fields OCR slice Field D31 Card power up status bit (Busy). D[30-24] reserved D23 ...
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HB28H016/D032/B064/B128MM2 Card Identification (CID) This register contains the card identification information used during the card identification procedure 128 bit wide register, one-time programmable by the provider. It was programmed at the manufacture. The CID is divided into ...
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Card Specific Data (CSD) The card specific data register describes how to access the card content. The CSD defines card operating parameters like maximum data access time, data transfer speed. The CSD Fields Name Field CSD structure CSD_STRUCTURE Spec version ...
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HB28H016/D032/B064/B128MM2 Name Field Write protect group size WP_GRP_SIZE Write protect group enable WP_GRP_ENABLE Manufacturer default ECC DEFAULT_ECC Write speed factor R2W_FACTOR Max. write data block length WRITE_BLK_LEN Partial blocks for write WRITE_BLK_PARTIAL 1 allowed Reserved — File format group FILE_FORMAT_GRP ...
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SPEC_VERS Defines the Spec version supported by the card. It includes the commands set definition and the definition of the card responses. The card identification procedure is compatible for all spec versions! SPEC Version SPEC_VERS “0011” The Spec version ...
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HB28H016/D032/B064/B128MM2 • TRAN_SPEED The following table defines the maximum data transfer rate TRAN_SPEED: Maximum Data Transfer Rate Definition TRAN_SPEED bit 2:0 6:3 7 These Hitachi MultiMediaCards support a transfer rate between 0 and 20 Mbit/s. The parameter TRAN_SPEED is 0x2A. ...
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READ_BLK_LEN The data block length is computed as 2 Data Block Length READ_BLK_LEN Block length byte bytes ...... ...... 2048 bytes 12–15 reserved The block ...
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... Therefore, the maximal capacity which can be coded is 4096*512*2048 = 4 GBytes. The following table shows the card capacity for each model. Model C_SIZE HB28H016MM2 0x7A7 HB28D032MM2 0x7A7 HB28B064MM2 0x7A7 HB28B128MM2 0x7A7 Rev.5.0, Jan. 2003, page DSR type no DSR implemented DSR implemented , (READ_BLK_LEN < 12) ...
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... VDD_R_CURR_MAX VDD_W_CURR_MAX 2:0 The parameter VDD_R_CURR_MAX and VDD_W_CURR_MAX are permanently assigned. The value of VDD_R_CURR_MAX and VDD_W_CURR_MAX for each model is following: Model HB28H016MM2 HB28D032MM2 HB28B064MM2 HB28B128MM2 For more details refer to Chapter “Characteristics”. HB28H016/D032/B064/B128MM2 Code for current consumption at 2 0 ...
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HB28H016/D032/B064/B128MM2 • C_SIZE_MULT This parameter is used for coding a factor MULT for computing the total device size (refer to “C_SIZE”). The factor MULT is defined as 2 Multiply Factor for the Device Size C_SIZE_MULT MULT ...
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DEFAULT_ECC Set by the card manufacturer and defines the ECC code which is recommended to use (e.g. the device is tested for). The value is set to ‘0’, indicating that no designated ECC is recommended. • R2W_FACTOR Defines the ...
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HB28H016/D032/B064/B128MM2 • WRITE_BLK_PARTIAL WRITE_BLK_PARTIAL defines whether partial block sizes can be used in block read and block write commands. WRITE_BLK_PARTIAL = 0 means that only the block size defined by WRITE_BLK_LEN can be used for block-oriented data transfers. WRITE_BLK_PARTIAL = ...
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ECC Defines the ECC code that was used for storing data on the card. This field is used by the host (or application) to decode the user data. The following table defines the field format. ECC ECC ECC type ...
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HB28H016/D032/B064/B128MM2 MultiMediaCard Communication All communication between host and cards is controlled by the host (master). The host sends commands and, depending on the command, receives a corresponding response from the selected card. In this chapter the commands to control these ...
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MultiMediaCard Each WP-group may have an additional write protection bit. The write protection bits are programmable via special commands (refer to Chapter “Commands”). The information about the availability is stored in the CSD. HB28H016/D032/B064/B128MM2 ERASE GROUP 0 Block 0 Block ...
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HB28H016/D032/B064/B128MM2 Commands The command set of the MultiMediaCard system is divided into classes corresponding to the type of card (see also [1]). These Hitachi MultiMediaCards support the following command classes: Command Classes (Class 0 to Class 2) Card command class ...
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The command transmission always starts with the MSB. Each command starts with a start bit and ends with a 7-bit CRC command protection field followed by an end bit. The length of each command frame is fixed to 48 bits ...
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HB28H016/D032/B064/B128MM2 Read, Write and Erase Time-out Conditions The times after which a time-out condition for read/write/erase operations occurs are (card independent) 10 times longer than the access/program times for these operations given below. A card shall complete the command within ...
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Basic Commands (class 0) and Read Stream Command (class 1) CMD index Type Argument CMD0 bc [31:0] stuff bits CMD1 bcr [31:0] OCR without busy CMD2 bcr [31:0] stuff bits CMD3 ac [31:16] RCA [15:0] stuff bits CMD4 bc [31:16] ...
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HB28H016/D032/B064/B128MM2 Block-Oriented Read Commands (class 2) CMD index Type Argument CMD16 ac [31:0] block length CMD17 adtc [31:0] data address CMD18 adtc [31:0] data address Notes: 1. The default block length is as specified in the CSD. These Hitachi MultiMediaCards ...
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Block-Oriented Write Commands (class 4) CMD index Type Argument CMD24 adtc [31:0] data address CMD25 adtc [31:0] data address CMD26 adtc [31:0] stuff bits CMD27 adtc [31:0] stuff bits Note: 1. The data transferred must not cross a physical block ...
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HB28H016/D032/B064/B128MM2 Erase Commands (class 5) CMD index Type Argument CMD32 ac [31:0] data address CMD33 ac [31:0] data address CMD34 ac [31:0] data address CMD35 ac [31:0] data address CMD36 ac [31:0] data address CMD37 ac [31:0] data address CMD38 ...
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Write Protection Commands (class 6) CMD index Type Argument CMD28 ac [31:0] data address CMD29 ac [31:0] data address CMD30 adtc [31:0] write protect data address Note write protection bits (representing 32 write protect groups starting at the ...
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HB28H016/D032/B064/B128MM2 Other Command CMD index Type Argument CMD5 reserved CMD6 reserved CMD8 reserved CMD14 reserved CMD19 reserved CMD21 … reserved CMD22 CMD31 reserved CMD39 Not supported CMD40 Not supported CMD41 reserved CMD43 … reserved CMD54 CMD55 ac [31:16] RCA [15:0] ...
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Card identification mode All the data communication in the card identification mode uses only the command line (CMD). Power on Idle state (idle) card is busy or host omitted voltage range CMD1 card looses bus Ready state (ready) CMD2 Identification ...
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HB28H016/D032/B064/B128MM2 their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification ...
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Data Transfer Mode When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f allows the host to get the Card Specific Data ...
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HB28H016/D032/B064/B128MM2 ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for block-oriented data transfer is preserved by a 16-bit CRC check sum (refer to Chapter “Cyclic Redundancy Check (CRC)”). • Stream read ...
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The read error is reported in the response to the stop transmission command. If the host sends a stop transmission command after the card transmits the last block of a ...
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HB28H016/D032/B064/B128MM2 The card will transfer the requested number of data blocks, terminate the transaction and return to transfer state. Stop command is not required at the end of this type of multiple block write, unless terminated with an error. In ...
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As described above for block write, the card will indicate that an erase is in progress by holding DAT low. The actual erase time may be quite long, and the host may choose to deselect the ...
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HB28H016/D032/B064/B128MM2 • SET_PWD Set new password to PWD • PWD_LEN: Defines the following password length (in bytes). • PWD: The password (new or currently used depending on the command). The data block size shall be defined by the ...
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If the PWD content equals to the sent password then the card will be locked and the card-locked status bit will be set in the status register. If the password is not correct then LOCK_UNLOCK_FAILED error bit will be set ...
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HB28H016/D032/B064/B128MM2 • State transition summary Table “Card State Transition Table” defines the card state transitions as a function of received command Card State Transition Table Current state Command idle 1 CRC fail —* Commands out of the — supported class(es) ...
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Current state Command idle Class4 CMD16 CMD23 CMD24 — CMD25 — CMD26 — CMD27 — Class5 CMD32 — CMD33 — CMD34 — CMD35 — CMD36 — CMD37 — CMD38 — Class6 CMD28 — CMD29 — CMD30 — Class7 CMD42 — ...
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HB28H016/D032/B064/B128MM2 Responses All responses are sent via command line (CMD), all data starts with the MSB. Format R1 (response command): response length 48 bit. 0 start bit The contents of the status field are described in Chapter “Status” Format R1b ...
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Status The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit status information which is stored in a local status register of each card to the host. The following table defines ...
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HB28H016/D032/B064/B128MM2 Status Bits Identifier Type Value 31 OUT_OF_RANGE ADDRESS_ERROR ’0’= no error 29 BLOCK_LEN_ERRO ERASE_SEQ_ERR ERASE_PARAM WP_VIOLATION ’0’= not protected ...
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Bits Identifier Type Value 16 CID_OVERWRITE ’0’= no error CSD_OVERWRITE 15 WP_ERASE_SKIP CARD_ECC_ S X DISABLED 13 ERASE_RESET S R 12:9 CURRENT_STATE BUFFER_EMPTY S X 7:6 reserved 5 APP_CMD S R ...
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HB28H016/D032/B064/B128MM2 Command Response Timings All timing diagrams use the following schematics and abbreviations: S: Start bit (= 0) T: Transmitter bit (Host = 1, Card = 0) P: One-cycle pull- End bit (= 1) Z: high impedance ...
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The host command and the card response are clocked out with the rising edge of the host clock. The delay between host command and card response is N for host command CMD3: Host command CMD S T content Host active ...
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HB28H016/D032/B064/B128MM2 • Last host command - next host command timing diagram After the last command, which does not force a response, has been sent, the host can continue sending the next command after at least N CC Host command CMD ...
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Stream read The data transfer starts N clock cycles after the end bit of the host command. The bus transaction is AC identical to that of a read block command (refer to Figure “Data Read Timing”). As the data ...
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HB28H016/D032/B064/B128MM2 • Stream write The data transfer starts N clock cycles after the card response to the sequential write command was WR received. The bus transaction is identical to that of a write block command (see Figure “Timing of The ...
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Reset GO_IDLE_STATE (CMD0) is the software reset command, which sets the MultiMediaCard into the Idle State independently of the current state. In the Inactive State the MultiMediaCard is not affected by this command. After power-on the MultiMediaCard is always in ...
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HB28H016/D032/B064/B128MM2 SPI Communication The SPI mode consists of a secondary communication protocol. This mode is a subset of the MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers. The ...
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Bus Transfer Protection Every MultiMediaCard token transferred on the bus is protected by CRC bits. In SPI mode, the MultiMediaCard offers a non-protected mode which enables systems built with reliable data links to exclude the hardware or firmware required for ...
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HB28H016/D032/B064/B128MM2 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Two types of multiple block read transactions are defined (the host can use either one at any time): • Open-ended Multiple block read The number of blocks for the read multiple ...
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Data in command Data out After a data block has been received, the card will respond with a data-response token. If the data block has been received without errors, it will be programmed. As long as ...
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HB28H016/D032/B064/B128MM2 failure in the data-response token and ignore any further incoming data blocks. The host must than abort the operation by sending the ‘Stop Tran’ token. If the host uses partial blocks whose accumulated length is not block aligned and ...
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Erase and Write Protect Management The erase and write protect management procedures in the SPI mode are identical to those of the MultiMediaCard mode. While the card is erasing or changing the write protection bits of the predefined sector list, ...
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HB28H016/D032/B064/B128MM2 Error Conditions Unlike the MultiMediaCard protocol, in the SPI mode the card will always respond to a command. The response indicates acceptance or rejection of the command. A command may be rejected not supported (illegal opcode), ...
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Commands and Arguments CMD index SPI mode Argument CMD0 Yes None CMD1 Yes None CMD2 No CMD3 No CMD4 No CMD5 reversed CMD6 reversed CMD7 No CMD8 reversed CMD9 Yes None CMD10 Yes None CMD11 No CMD12 Yes None CMD13 ...
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HB28H016/D032/B064/B128MM2 CMD index SPI mode Argument CMD24 Yes [31:0] data address CMD25 Yes [31:0] data address CMD26 No CMD27 Yes None CMD28 Yes [31:0] data address CMD29 Yes [31:0] data address CMD30 Yes [31:0] write protect data address CMD31 reserved ...
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CMD index SPI mode Argument CMD41 reserved CMD42 Yes [31:0] stuff bits CMD43... reserved CMD54 CMD55 (Yes) [31:16] RCA [15:0] stuff bits CMD56 (Yes) [31:1] stuff bits [0:0] RD/WR* CMD57 reserved CMD58 Yes None CMD59 Yes [31:1] stuff bits [0:0] ...
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HB28H016/D032/B064/B128MM2 6. “MultiMediaCard system specification Version 3.1” does not support these commands, but these Hitachi MultiMediaCards support them to keep backward compatibility with former MultiMediaCard series. 7. ‘1’ the host gets a block of data from the card. ‘0’ the ...
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Format R2 This response token is two bytes long and sent as a response to the SEND_STATUS command. The format is given in Figure “R2 Response Format”. 1. Byte The first byte is identical to the ...
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HB28H016/D032/B064/B128MM2 • Format R3 This response token is sent by the card when a READ_OCR command is received. The response length is 5 bytes (refer to Figure “R3 Response Format”). The structure of the first (MSB) byte is identical to ...
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Data Error Token If a read operation fails and the card cannot provide the required data, it will send a data error token instead. This token is one byte long and has the following format: The 4 least significant bits ...
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HB28H016/D032/B064/B128MM2 Clearing Status Bits As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different formats: response R1, response R2 and data error token (the same bits may exist in multiple response ...
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Included Identifier in resp Type Illegal command Card ECC failed DataErr CC error DataErr Error DataErr WP erase skip Lock/Unlock R2 E ...
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HB28H016/D032/B064/B128MM2 SPI Bus Timing All timing diagrams use the following schematics and abbreviations: H: Signal is high (logical ‘1’) L: Signal is low (logical ‘0’) X: Don’t care Z: High impedance state (-> Repeater Busy: Busy Token ...
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Card Response to Host Command Datain Dataout bytes response • ...
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HB28H016/D032/B064/B128MM2 • Single Block Write Datain Write command Dataout ...
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Error Handling MultiMediaCards are defined as error free devices or as devices with a defined maximum bit error rate (with external error correction circuitry). To correct defects in the memory field of the cards the system may include error correction ...
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HB28H016/D032/B064/B128MM2 Cyclic Redundancy Check (CRC) The CRC is intended for protecting MultiMediaCard commands, responses and data transfer against transmission errors on the MultiMediaCard bus. One CRC is generated for every command and checked for every response on the CMD line. ...
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Power Supply Power Supply Decoupling The and V lines supply the card with operating voltage. For this, decoupling capacitors for SS1 SS2 CC buffering current peak are used. These capacitors are placed on the bus side corresponding ...
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HB28H016/D032/B064/B128MM2 Power on Each card has its own power on detection circuitry which puts the card into a defined state after the power- on. No explicit reset signal is necessary. The cards can also be reset by a special software ...
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V Bus master supply voltage 2.7 V 2.0 V Power up time Supply ramp up time Initialization sequence Initialization delay: The maximum of 1 msec, 74 clock cycles and supply ramp up time • After power up (including hot ...
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HB28H016/D032/B064/B128MM2 Short Cut Protection The MultiMediaCards can be inserted/removed into/from the bus without damage. If the card insertion/removal is occured during card operation (read/write), the data in the MultiMediaCard would be broken. If one of the supply pins (V a ...
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Characteristics This chapter defines following characteristics: • Temperature characteristics • Electrical characteristics Temperature Characteristics Parameter Symbol Storage temperature Tstg Operating temperature Topr Junction temperature Tj Electrical Characteristics In this chapter the electrical characteristics for these Hitachi MultiMediaCards are defined in ...
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HB28H016/D032/B064/B128MM2 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not ...
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Recommended Operating Conditions The recommended operating conditions define the parameter ranges for optimal performance and durability of these Hitachi MultiMediaCards. Parameter Supply voltage Inputs Low-level input voltage V High-level input voltage V Outputs High-level output current Low-level output current Clock ...
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... Chapter “Recommended Operating Conditions”). Parameter High speed supply HB28H016MM2 current HB28D032MM2 HB28B064MM2 HB28B128MM2 Minimal supply HB28H016MM2 current HB28D032MM2 HB28B064MM2 HB28B128MM2 Typical supply Single Block Read current Single Block Write All digital inputs Input leakage current (Including I/O current) All outputs High-level output ...
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Clock Input Valid data Output : Invalid Timing Diagram of Data Input and Output The access time ( divided into two parts: AT • The synchronous access time. This time defines the time of the maximum ...
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HB28H016/D032/B064/B128MM2 Access Time Parameter Synchronous access delay cycles Synchronous access delay Asynchronous access delay Memory access time Note: 1. Refer to Chapter “Time-out Condition”. In the CSD are two fields to code the asynchronous and the synchronous access delay time: ...
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Abbreviations and Terms Abbreviations Terms <n> Argument of a command or data field. CMD<n> MultiMediaCard bus command <n>. See Command. PP Push Pull, output driver type with low impedance driver capability for 0 and 1. OD Open Drain, output driver ...
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HB28H016/D032/B064/B128MM2 Abbreviations Terms CIN Card individual number. CRC Cyclic redundancy check. ECC Error correction code. G(x) Generator polynomial of error correction/check code. TAC Asynchronous access delay NSAC Number of synchronous access cycles to be added to the access delay f ...
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Physical Outline Front Back HB28H016/D032/B064/B128MM2 As of January, 2002 Tolerance: 0.1 mm 27.3 25.9 4.0 2.1 3 × R1.0 4.5 Min 1.2 Max × R0.5 4.0 32.0 Rev.5.0, Jan. 2003, page 87 ...
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HB28H016/D032/B064/B128MM2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may ...