K4H560438E-GCC4 SAMSUNG [Samsung semiconductor], K4H560438E-GCC4 Datasheet
K4H560438E-GCC4
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K4H560438E-GCC4 Summary of contents
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... DDR SDRAM 256Mb E-die (x4, x8) 256Mb E-die DDR 400 SDRAM Specification 60Ball FBGA (x4/x8) Revision 1.1 DDR SDRAM Rev. 1.1 September. 2003 ...
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... DDR SDRAM 256Mb E-die (x4, x8) 256Mb E-die Revision History Revision 1.0 (July, 2003) - First release Revision 1.1 (September, 2003) - Modified DDR SDRAM Spec Items & Test Conditions DDR SDRAM Rev. 1.1 September. 2003 ...
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... DM for write masking only (x4, x8) • Auto & Self refresh • 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8 • 60Ball FBGA package Ordering Information Part No. K4H560438E-GCCC K4H560438E-GCC4 K4H560838E-GCCC K4H560838E-GCC4 Operating Frequencies - CC(DDR400@CL=3) Speed @CL3 200MHz CL-tRCD-tRP *CL : CAS Latency Org ...
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... DDR SDRAM 256Mb E-die (x4, x8) Ball Description (Bottom 64M x 4bit 1 VSSQ VDDQ VSSQ 3 VSS DQ3 VDD DQ0 VSSQ VDDQ 9 VDDQ NC NC 32M x 8bit 1 VSSQ DQ7 VDDQ VSSQ 3 VSS DQ6 DQ5 VDD DQ1 DQ2 8 DQ0 ...
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... DDR SDRAM 256Mb E-die (x4, x8) Package Physical Dimension 8.0 0± 0.10 TOP VIEW ( Unit : mm ) ENCAPSULANT AREA 0.35 ± 0.05 π 0.45 1.10± 0.10 60Ball FBGA Package Dimension DDR SDRAM 8.00 ± 0.10 0. 6.40 0. 3.20 1.60 1. 0.80 (0.90) (0.90) ± 0.05 (1.80) BOTTOM VIEW Rev. 1.1 September. 2003 ...
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... DDR SDRAM 256Mb E-die (x4, x8) Block Diagram (64Mbit x 4 Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE / 32Mbit Banks) x4/8 CK, CK Data Input Register Serial to parallel x8/16 8Mx8/ 4Mx16 8Mx8/ 4Mx16 8Mx8/ 4Mx16 8Mx8/ 4Mx16 Column Decoder Latency & Burst Length ...
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... DDR SDRAM 256Mb E-die (x4, x8) Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input DM Input BA0, BA1 Input 12] Input DQ I/O DQS I VDDQ Supply VSSQ Supply VDD Supply VSS Supply VREF Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...
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... DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 CKEn CS ...
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... Banks / 8M x 8Bit x 4 Banks Banks Double Data Rate SDRAM General Description The K4H560438E / K4H560838E / is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 16,785,216 / 4x 8,388,608 words by 4/ 8bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... DDR SDRAM 256Mb E-die (x4, x8) DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles high between valid commands. ...
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... CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK Setup : RA0 A2 RA1 A3 RA2 N RA3 N N Read : RA0 A2 RA1 A3 RA2 N RA3 repeat the same timing with random address changing *50% of data changing at every transfer Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP 64Mx4 (K4H560438E), 32Mx8 (K4H560838E) CC(DDR400@CL=3) 105 130 4 ...
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... DDR SDRAM 256Mb E-die (x4, x8) AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...
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... DDR SDRAM 256Mb E-die (x4, x8) Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...
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... DDR SDRAM 256Mb E-die (x4, x8) AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write to read command delay Clock cycle time ...
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... DQS will be tran sitioning from High logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 7. For command/address input slew rate ≥ 0.5 V/ns 8. For CK & ...
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... DDR SDRAM 256Mb E-die (x4, x8) System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor- mance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM ...
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... DDR SDRAM 256Mb E-die (x4, x8) System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. Output Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. Output Figure 2 : Pulldown slew rate test load c ...
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... DDR SDRAM 256Mb E-die (x4, x8) j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions ...