54F402 NSC [National Semiconductor], 54F402 Datasheet - Page 4

• Manufacturer Part Number: 54F402
• Description: Serial Data Polynomial Generator/Checker
• Manufacturer: NSC [National Semiconductor]

Applications
In addition to polynomial selection there are four other ca-
pabilities provided for in the ’F402 ROM The first is set or
clear selectability The sixteen internal registers have the
capability to be either set or cleared when P is brought
LOW This set or clear capability is done in four groups of 4
(see Table II P
determining the polarity of the check word As is the case
with the Ethernet polynomial the check word can be invert-
ed when it is appended to the data stream or as is the case
with the other polynomials the residue is appended with no
inversion Thirdly the ROM contains a bit (C
to select the RFB input instead of the SEI input to be fed
into the LSB This is used when the polynomial selected is
actually a residue (least significant) stored in the ROM
which indicates whether the selected location is a polynomi-
al or a residue If the latter then it inhibits the RFB input
As mentioned previously upon a successful data transmis-
sion the CRC register has a zero residue There is an ex-
ception to this however with respect to the Ethernet poly-
nomial This polynomial upon a successful data transmis-
sion has a non-zero residue in the CRC register (C7 04 DD
7B)
locations have been preloaded with the residue so that by
selecting these locations and clocking the device one addi-
tional time after the last check bit has been entered will
result in zeroing the CRC register In this manner a no-error
indication is achieved
With the present mix of polynomials the largest is 56
der requiring four devices while the smallest is 16
requiring just one device In order to accommodate multi-
plexing between high order polynomials (X 16
lower order polynomials a location of all zeros is provided
This allows the user to choose a lower order polynomial
even if the system is configured for a higher order one
16
In order to provide a no-error indication two ROM
Select Code
0
–P
3
) The second ROM capability (C
C
D
E
F
B
A
0
7
3
2
4
8
5
9
1
6
P
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
3
P
1
0
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
) which is used
2
th
order) and
th
0
P
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
) is in
order
th
1
or-
TABLE II
P
4
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
The ’F402 expandable CRC generator checker contains 6
popular CRC polynomials 2-16
48
shows the ’F402 connected for a 56
Also shown are the input patterns for other polynomials
When the ’F402 is used with a gated clock disabling the
clock in a HIGH state will ensure no erroneous clocking
occurs when the clock is re-enabled Preset and Master Re-
set are asynchronous inputs presetting the register to S or
clearing to 1s respectively (note Ethernet residue and 56
Order select code 8 LSB are exceptions to this)
To generate a CRC the pattern for the selected polynomial
is applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH data is applied
to D input output data is on D CW When the last data bit
has been entered CWG is set LOW and the register is
clocked for n bits (where n is the order of the polynomial)
The clock may now be stopped if desired (holding CWG
LOW and clocking the register will output zeros from D CW
after the residue has been shifted out)
To check a CRC the pattern for the selected polynomial is
applied to the S inputs the register is preset or cleared as
required clock is enabled CWG is set HIGH the data
stream including the CRC is applied to D input When the
last bit of the CRC has been entered the ER output is
checked HIGH
clock may now be stopped if desired
To implement polynomials of lower order than 56
the number of packages required for the order of polynomial
and apply the pattern for the selected polynomial to the S
inputs (0000 on S inputs disables the package from the
feedback chain)
th
C
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
Order and 1-56
2
C
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
e
error free data LOW
th
C
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Order The application diagram
th
Polynomial
S
Ethernet
Polynomial
Ethernet
Residue
CRC-16
CRC-CCITT
56th
Order
48th
Order
32nd
Order
e
Order 2-32
0
th
e
Order polynomial
corrupt data The
nd
Order 1-
th
select
th