STI5105_08 STMICROELECTRONICS [STMicroelectronics], STI5105_08 Datasheet

STI5105_08

Manufacturer Part Number

STI5105_08

Description

High-performance advanced SD decoder for set-top box

Manufacturer

STMICROELECTRONICS [STMicroelectronics]

Datasheet

1.STI5105_08.pdf (5 pages)

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November 2008

For further information contact your local STMicroelectronics sales office.

Features

■

Enhanced ST20 32-bit VL-RISC CPU

– 200 MHz, single cycle cache, 4 Kbyte

Unified memory interface

– Up to133 MHz,16-bit wide DDR interface

Programmable flash memory interface

– SRAM, peripheral, Flash, SFlash™ support

– Support for low-cost DVB-CI and ATAPI

Programmable transport interface (PTI)

– Single transport stream input

– Support for DVB transport streams

– Integrated DVB, ICAM descramblers

MPEG-2 MP@ML video decoder

– Fully programmable horizontal and vertical

Graphics/display

– Advanced blitter base compositor

– 8 bpp CLUT graphics, 256 x 30 bits

– 16 bpp true color graphics, RGB565,

– Alpha blending, antialiasing, antiflutter,

– 2D paced blitter engine with fill function

instruction cache, 4 Kbyte data cache, 2

Kbyte SRAM

SRCs

(AYCbCr) CLUT entries

ARGB1555, ARGB4444 formats with link-list

control

antiflicker filters

High-performance advanced SD decoder for set-top box

STV0360

COFDM

+ tuner

STV0297

QAM demodulator

+ tuner

STV0299

and STV6110A

tuner

STV0360

COFDM

+ tuner

STV0297

QAM demodulator

+ tuner

STV0299

and STB6000

tuner

Smart

card

Rev 1

DRAM

■

STi5105

PAL/NTSC/SECAM encoder

– RGB, CVBS, Y/C and YUV outputs with four

– Encoding of CGMS, Teletext, WSS, VPS,

Audio subsystem

– MPEG-1 layers I/II

– Simultaneous MPEG audio decode and

– IEC958/IEC1937 digital audio output

– Integrated stereo audio DAC system

Central DMA controller

On-chip peripherals

– Two ASCs (UARTs) with Tx and Rx FIFOs

– Three 8-bit banks of parallel I/O and one 7-

– One smartcard interface and clock

– Two SSCs for I²C/SPI master/slave

– Infrared transmitter/receiver

– Integrated VCXO

– Low-power/RTC/watchdog controller

JTAG/TAP interface

Package 24 mm x 24 mm LQFP216 or

23 mm x 23 mm BGA.

RX/TX

NOR

Flash

10-bit DAC outputs. RGB/CVBS or

YUV/CVBS or YC/CVBS

close caption

output of Dolby streams on S/PDIF

interface

bit bank

generator

interfaces

Video

buffer

Audio

buffer

STi5105

Data Brief

www.st.com

1/5

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STI5105_08 Summary of contents

Page 1

High-performance advanced SD decoder for set-top box Features ■ Enhanced ST20 32-bit VL-RISC CPU – 200 MHz, single cycle cache, 4 Kbyte instruction cache, 4 Kbyte data cache, 2 Kbyte SRAM ■ Unified memory interface – Up to133 MHz,16-bit wide ...

Page 2

Description 1 Description STMicroelectronics sets a new standard for performance, price and integration in the single chip MPEG-2 set-top box decoder market with the introduction of the STi5105. This highly integrated solution targets mass market STBs, offers increased performance over ...

Page 3

STi5105 2 Ordering information Table 1. Ordering information Order code STi5105ALC STi5105AYC Ordering information Packaging LQFP216 BGA 3/5 ...

Page 4

Revision history 3 Revision history Table 2. Document revision history Date 24-Nov-08 4/5 Revision 1 Initial release STi5105 Changes ...

Page 5

STi5105 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...

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