MC74ACT253DG ON Semiconductor, MC74ACT253DG Datasheet - Page 2

• Manufacturer Part Number: MC74ACT253DG
• Description: IC MUX DUAL 4INPUT 3ST 16-SOIC
• Manufacturer: ON Semiconductor
• Series: 74ACTr
• Type: Multiplexerr

Specifications of MC74ACT253DG

• Circuit: 2 x 4:1
• Independent Circuits: 1
• Current - Output High, Low: 24mA, 24mA
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4−input multiplexers with 3−state outputs. They select two
bits from four sources selected by common Select inputs (S
S
Enable (OE
outputs to a high impedance (High Z) state. This device is the
logic implementation of a 2−pole, 4−position switch, where
the position of the switch is determined by the logic levels
TRUTH TABLE
Address inputs S
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
1
S
The MC74AC253/74ACT253 contains two identical
H
H
H
H
). The 4−input multiplexers have individual Output
X
L
L
L
L
Select
Inputs
0
S
X
H
H
H
H
L
L
L
L
1
a
FUNCTIONAL DESCRIPTION
, OE
0
and S
I
H
X
L
X
X
X
X
X
X
0
OE
b
) inputs which, when HIGH, force the
b
1
Data Inputs
are common to both sections.
I
H
X
X
X
X
X
X
X
L
1
I
3b
NOTE:
I
X
X
X
X
X
H
X
X
L
2
I
2b
Z
This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
I
H
X
X
X
X
X
X
X
L
3
b
I
1b
Output
Enable
OE
H
L
L
L
L
L
L
L
L
I
0b
Figure 3. Logic Diagram
Outputs
http://onsemi.com
H
H
H
H
Z
Z
L
L
L
L
S
0
0
,
2
S
supplied to the two select inputs. The logic equations for the
outputs are shown:
Z
Z
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3−state devices
whose outputs are tied together are designed so that there is
no overlap.
1
a
b
If the outputs of 3−state devices are tied together, all but
= OE
= OE
a •
b •
I
S
S
3a
0
1
OE
(I
(I
0a •
0b •
I
I
a
Figure 2. Logic Symbol
2a •
2b •
I
0a
S
S
S
S
1 •
1 •
I
2a
I
1 •
1 •
1a
S
S
S
S
0
0
I
Z
+I
+I
0
0
2a
a
Z
+I
+I
1a •
1b •
a
I
3a •
3b •
3a
I
1a
S
S
S
S
I
1 •
1 •
0b
1 •
1 •
S
S
I
Z
S
S
0
0
1b
b
+
+
0
0
I
)
)
0a
I
2b
I
3b
OE
OE
b
a