CY7C09089 Cypress Semiconductor Corporation., CY7C09089 Datasheet

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CY7C09089

Manufacturer Part Number
CY7C09089
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheets

Specifications of CY7C09089

Case
QFP
Date_code
05+

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www.DataSheet4U.com
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25/0251
4
Cypress Semiconductor Corporation
Document #: 38-06039 Rev. *A
Features
Notes:
1.
2.
3.
• True dual-ported memory cells which allow simulta-
• Six Flow-Through/Pipelined devices
• Three Modes
• Pipelined output mode on both ports allows fast 100-
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5
Logic Block Diagram
R/W
OE
CE
CE
FT/Pipe
I/O
A
CLK
ADS
CNTEN
CNTRST
neous access of the same memory location
MHz cycle time
(max.)
— 64K x 8/9 organizations (CY7C09089/189)
— 128K x 8/9 organizations (CY7C09099/199)
— Flow-Through
— Pipelined
— Burst
0
See page 7 for Load Conditions.
I/O
A
–A
0L
0L
1L
0
L
–A
0
L
L
L
–I/O
–I/O
[3]
15/16L
15
L
L
for 64K; and A
7
[2]
L
7/8L
for x8 devices; I/O
16/17
0
–A
For the most recent information, visit the Cypress web site at www.cypress.com
16
0
for 128K devices.
–I/O
8/9
0/1
0/1
1
0
1
Counter/
Address
Register
8
Decode
for x9 devices.
0
[1]
/7.5/9/12 ns
3901 North First Street
Control
I/O
True Dual-Ported
Synchronous Dual-Port Static RAM
RAM Array
• Low operating power
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT70908
and IDT709089
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
Control
I/O
San Jose
0
Counter/
Register
Address
Decode
CA 95134
0/1
1
1
0
0/1
64K/128K x 8/9
8/9
Revised December 27, 2002
CY7C09089/99
CY7C09189/99
16/17
I/O
408-943-2600
A
0R
CNTRST
0
FT/Pipe
CNTEN
–A
–I/O
ADS
[3]
15/16R
R/W
CLK
CE
CE
OE
[2]
7/8R
0R
1R
R
R
R
R
R
R
R

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