MC74HC138ADTR2G ON Semiconductor, MC74HC138ADTR2G Datasheet

no-image

MC74HC138ADTR2G

Manufacturer Part Number
MC74HC138ADTR2G
Description
IC DECODER/DEMUX 1:8 16-TSSOP
Manufacturer
ON Semiconductor
Series
74HCr
Type
Decoder/Demultiplexerr
Datasheet

Specifications of MC74HC138ADTR2G

Circuit
1 x 3:8
Independent Circuits
1
Current - Output High, Low
5.2mA, 5.2mA
Voltage Supply Source
Single Supply
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Product
Decoders, Encoders, Multiplexers & Demultiplexers
Logic Family
74HC
Number Of Bits
3
Number Of Lines (input / Output)
1.0 / 8.0
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Number Of Input Lines
1.0
Number Of Output Lines
8.0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC74HC138ADTR2G
Manufacturer:
ON
Quantity:
12 500
MC74HC138A
1-of-8 Decoder/
Demultiplexer
High−Performance Silicon−Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
active−low outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 10
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC74HC138A is identical in pinout to the LS138. The device
The HC138A decodes a three−bit Address to one−of−eight
Standard No. 7A
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Chip Complexity: 100 FETs or 29 Equivalent Gates
Pb−Free Packages are Available*
m
A
1
16
16
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
16
16
1
1
1
1
ORDERING INFORMATION
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
http://onsemi.com
CASE 751B
CASE 948F
SOEIAJ−16
TSSOP−16
DT SUFFIX
CASE 648
CASE 966
N SUFFIX
D SUFFIX
F SUFFIX
SOIC−16
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
Publication Order Number:
16
16
1
1
16
1
MC74HC138AN
MC74HC138A/D
DIAGRAMS
AWLYYWWG
16
1
MARKING
HC138AG
AWLYWW
74HC138A
ALYWG
ALYWG
138A
HC
G

Related parts for MC74HC138ADTR2G

MC74HC138ADTR2G Summary of contents

Page 1

... Chip Complexity: 100 FETs or 29 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 10 http://onsemi.com PDIP− ...

Page 2

... H = high level (steady state low level (steady state don’t care ORDERING INFORMATION Device MC74HC138ANG MC74HC138ADG MC74HC138ADR2 MC74HC138ADR2G MC74HC138ADTR2 MC74HC138ADTR2G MC74HC138AFG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ADDRESS ...

Page 3

MAXIMUM RATINGS Symbol Parameter V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) out I DC Input Current, per Pin Output Current, per ...

Page 4

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High−Level Input IH Voltage V Maximum Low−Level Input IL Voltage V Minimum High−Level Output OH Voltage Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

VALID INPUT A 50% t PLH OUTPUT Y 50% Figure 90% INPUT 50% 10% CS2, CS3 t PHL 90% 50% OUTPUT Y 10% t THL Figure 3. ADDRESS INPUTS A0, A1, A2 (Pins Address ...

Page 6

EXPANDED LOGIC DIAGRAM CS3 4 CS2 6 CS1 http://onsemi.com ...

Page 7

0.25 (0.010) M −A− −T− SEATING PLANE 0.25 (0.010 PACKAGE DIMENSIONS PDIP−16 N ...

Page 8

K 16X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING D PLANE PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

Related keywords