IDT7290820PQF IDT, Integrated Device Technology Inc, IDT7290820PQF Datasheet - Page 7

• Manufacturer Part Number: IDT7290820PQF
• Description: IC DGTL SW 2048X2048 100-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r
• Type: Multiplexerr

Specifications of IDT7290820PQF

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 7290820PQF

maximum non-blocking switching data rate, the two DR bits in the IMS register
are used. Following are the possible configurations:
16-input/16-output data streams each having 32, 64 Kbit/s channels each. This
mode requires a CLK of 4.096 MHz and allows a maximum non-blocking
capacity of 512 x 512 channels.
16-input/16-output data streams each having 64, 64 Kbit/s channels each. This
mode requires a CLK of 8.192 MHz and allows a maximum non-blocking
capacity of 1,024 x 1,024 channels.
16-input/16-output data streams each having 128, 64 Kbit/s channels each. This
mode requires a CLK of 16.384 MHz and allows a maximum non-blocking
capacity of 2,048 x 2,048 channels.
between different serial data rates and the master clock frequencies.
INPUT FRAME OFFSET SELECTION
streams to be offset with respect to the output stream channel alignment (i.e. F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
data is often delayed, this feature is useful in compensating for the skew between
clocks.
frame input offset registers (FOR). The maximum allowable skew is +4.5 master
clock (CLK) periods forward with resolution of 1/2 clock period. The output frame
offset cannot be offset or adjusted. See Figure 5, Table 11 and 12 for delay offset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
different data input delays with respect to the frame pulse F0i.
bit low for at least one frame. When the SFE bit in the IMS register is changed
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Serial Interface
The IDT7290820 can operate at different speeds. To configure the
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with
Table 1 summarizes the switching configurations and the relationship
Input frame offset selection allows the channel alignment of individual input
Each input stream can have its own delay offset value by programming the
The IDT7290820 provides the frame evaluation (FE) input to determine
A measurement cycle is started by setting the start frame evaluation (SFE)
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Data Rate
Master Clock Required
16.384
(MHz)
4.096
8.192
Matrix Channel
1,024 x 1,024
2,048 x 2,048
512 x 512
Capacity
7
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurement cycle started.
is evaluated against the falling edge of the ST-BUS
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 10 & Figure 4 for the description of the frame alignment register.
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
connection memory block in two frames. To set bits 11 to 15 of every connection
memory location, first program the desired pattern in bits 5 to 9 of the IMS register.
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on the per-channel basis. For voice applications, variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
delay selected in the V/C bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT7290820 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if input
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the IDT7290820 in the
variable delay mode.
In ST-BUS
This feature is not available when the WFP Frame Alignment mode is
The IDT7290820 provides users with the capability of initializing the entire
The block programming mode is enabled by setting the memory block
The loopback control (LPBK) bit of each connection memory location allows
If the LPBK bit is high, the associated TX output channel data is internally
The switching of information from the input serial streams to the output serial
The delay through the device varies according to the type of throughput
In this mode, the delay is dependent only on the combination of source and
®
mode, the falling edge of the frame measurement signal (FE)
COMMERCIAL TEMPERATURE RANGE
®
frame pulse. In GCI mode,