74HC153D,652 NXP Semiconductors, 74HC153D,652 Datasheet - Page 10

• Manufacturer Part Number: 74HC153D,652
• Description: IC MULTIPLEXER DUAL 4INP 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: Multiplexerr

Specifications of 74HC153D,652

• Package / Case: 16-SOIC (3.9mm Width)
• Circuit: 2 x 4:1
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: 74HC
• Number Of Lines (input / Output): 12.0 / 2.0
• Propagation Delay Time: 14 ns
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 12.0
• Number Of Output Lines: 2.0
• Power Dissipation: 500 mW
• Logical Function: Mux
• Configuration: 2 x 4:1
• Number Of Inputs: 8
• Number Of Outputs: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1404-5; 74HC153D; 933714050652

Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND