FSTD16211MTDX Fairchild Semiconductor, FSTD16211MTDX Datasheet - Page 4

• Manufacturer Part Number: FSTD16211MTDX
• Description: IC SWITCH BUS 24BIT TTL 56TSSOP
• Manufacturer: Fairchild Semiconductor
• Type: Bus Switchr

Specifications of FSTD16211MTDX

• Circuit: 12 x 1:1
• Independent Circuits: 2
• Voltage Supply Source: Single Supply
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Number Of Switches: Dual
• Propagation Delay Time: 0.25 ns at 4.5 V to 5.5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Logic Family: FST
• Mounting Style: SMD/SMT
• On Resistance (max): 35 Ohms
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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t
t
t
C
C
PHL
PZH
PHZ
AC Electrical Characteristics
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Note 10: T
AC Loading and Waveforms
Note: Input driven by 50
Note: CL includes load and stray capacitance
Note: Input PRR
IN
I/O
Symbol
, t
, t
, t
Symbol
PLH
PZL
PLZ
A
Propagation Delay Bus to Bus (Note 9)
Output Enable Time
Output Disable Time

25
q
Control Pin Input Capacitance
Input/Output Capacitance
C, f
1.0 MHz, t
:
1 MHz, Capacitance is characterized but not tested.
source terminated in 50
Parameter
(Note 10)
W
500 ns
Parameter
:
C
L
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
T
A
Min
50pF, RU
1.5
1.5
V
CC

40
Typ
3.5
5.5
q
4.5 – 5.5V
C to
RD

4
85
Max
0.25
5.5
6.5
q
500
C,
:
Max
Units
ns
ns
ns
V
V
V
V
V
I
I
I
I
I
Units
pF
pF
OPEN
7V for t
OPEN for t
7V for t
OPEN for t
PZL
PLZ
Conditions
PZH
PHZ
V
V
CC
CC
, OE
5.0V
Conditions
5.0V
Number
Figures
Figures
Figures
Figure
1, 2
1, 2
1, 2