AM79C864AKCW AMD [Advanced Micro Devices], AM79C864AKCW Datasheet - Page 21

• Manufacturer Part Number: AM79C864AKCW
• Description: Physical Layer Controller With Scrambler (PLC-S)
• Manufacturer: AMD [Advanced Micro Devices]

PLC-S Control Register C (PLC_CNTRL_C)
PLC_CNTRL_C has address OA (hex). It is readable
and writeable. Bits 1 through 15 are cleared with the as-
sertion of RST. Bit 0 (CIPHER_ENABLE) assumes the
same value as SCRM after RST is asserted.
(Hex)
Addr
15–14 RESERVED
13–12 SDOFF_TIMER
11–10 SDON_TIMER
0A
9–8
5–2
Bit
7
6
1
0
15
Name
FOTOFF _CTRL
SDON_ENABLE
SDOFF_ENABLE
RESERVED
CIPHER_LPBCK
CIPHER_ENABLE
RESERVED
14
SDOFF_
TIMER
13
SDOFF_
TIMER
12
Definition
These two bits are reserved for diagnostic purposes and must be 0 for normal operation.
These two bits are used to select the timing values shown for deasserting Signal_Detect
ENABLE bit is set and scrambler/descrambler is enabled either (by SCRM or CIPHER_
ENABLE)
00=0.76 s
01=1.32 s
10=2.52 s
11=5.12 s
These two bits are used to select the timing values shown for asserting Signal_Detect if SDON_
ENABLE bit is set and scrambler/descrambler is enabled either by hardware or software.
00=0.84 s
01=1.32 s
10=2.52 s
11=5.12 s
These two bits are used to control the assertion of FOTOFF signal of PLC-S if scrambler/
descrambler is enabled either (by SCRM or CIPHER_ENABLE). The following timing delays
are with respect to the time from which PLC-S output scrambled Quiet symbols on TDAT lines.
00=Timer is bypassed (i.e., FOTOFF is asserted at the same time when scrambled Quiet
symbols are output on TDAT lines)
01=30 s delay
10=50 s delay
11=FOTOFF is never asserted
If this bit is set and scrambler/descrambler is enabled (by SCRM or CIPHER_ENABLE), then
SDON_TIMER bits (11–10) will determine the delay for asserting the Signal_Detect signal.
During this time, the descrambler is allowed to acquire synchronization of its input stream.
If this bit is set and scrambler/descrambler is enabled (bySCRM or CIPHER_ENABLE ), then
SDOFF_TIMER bits (13–12) will determine the delay for deasserting the Signal_Detect signal.
Bits 5–2 are reserved and should be set to 0.
If this bit is set, then the output of the scrambler is looped back to the input of the
descrambler (within PLC-S).
This bit is used to enable and disable the scrambler/descrambler function if SCRM (pin #41)
is not asserted. If SCRM is asserted, this bit is automatically set to 1. If SCRM is not
asserted, the value of this bit is determined by software. The default state (SCRM not
asserted) is 0.
SDON_
TIMER
11
SDON_
TIMER
10
Table 4. PLC_CNTRL_C
P R E L I M I N A R Y
FOTOFF_
CTRL
PLC_CNTRL_C
Am79C864A
9
FOTOFF_
CTRL
8
The PLC_CNTRL_C register bit assignments are listed
in Table 4.
SDON_
ENABLE
7
SDOFF_
ENABLE
6
5
4
RESERVED
3
2
CIPHER_
LPBCK
1
AMD
15535B-8
CIPHER_
ENABLE
3-23
0