MT88L70AC MITEL [Mitel Networks Corporation], MT88L70AC Datasheet - Page 2

• Manufacturer Part Number: MT88L70AC
• Description: 3 Volt Integrated DTMF Receiver
• Manufacturer: MITEL [Mitel Networks Corporation]

MT88L70
4-24
Pin Description
11-
18
10
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Pin #
12-
20
10
15
17
18
19
20
16
11
7,
1
2
3
4
5
6
8
9
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the
Name
OSC1 Clock (Input).
OSC2 Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
St/GT
PWDN
TOE
OSC2
V
INH
IN+
V
StD
ESt
V
OSC1
GS
NC
IN-
VRef
VSS
Ref
DD
SS
INH
IN+
GS
IN-
18 PIN CERDIP/PDIP/SOIC
Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.
Steering Input/Guard time (Output) Bidirectional. A voltage greater than V
No Connection.
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output). Nominally V
5 and Figure 6).
Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.
pin input is internally pulled down.
completes the internal oscillator circuit.
Ground (Input). 0V typical.
Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
St causes the device to register the detected tone pair and update the output latch. A
voltage less than V
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
Positive power supply (Input). +3V typical.
1
2
3
4
5
6
7
8
9
TSt
.
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
TSt
frees the device to accept a new tone pair. The GT output acts to
Figure 2 - Pin Connections
Description
PWDN
DD
OSC1
OSC2
VRef
VSS
INH
IN+
/2 is used to bias inputs at mid-rail (see Figure
GS
NC
IN-
20 PIN SSOP/TSSOP
10
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
TSt
detected at