EPXA4 ALTERA [Altera Corporation], EPXA4 Datasheet
EPXA4
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EPXA4 Summary of contents
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... Altera Corporation ES-EPXA4-1.2 Excalibur EPXA4 Devices Figure 1) Devices. Revision Number Known errata for the EPXA4 device—detailed in this document Known errata for the ARM922T processor provided by ARM Ltd.— detailed in Appendix A of this document Expansion bus interface (EBI) Dual-port SRAM (DPRAM) ...
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EBI This section provides further information about errata in the EBI. 1.1 Locked 16-Beat Incrementing Bursts A locked INCR16 transfer can cause the EBI to read from a peripheral twice. This can cause erroneous behavior if the peripheral contains read- ...
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Locking Mechanism is Non-Functional Using the DPRAM locking mechanism for simultaneous accesses from the stripe and PLD results in incorrect memory accesses. Simultaneous accesses to different addresses are not affected. Work Around Do not use the DPRAM locking feature. ...
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... Excalibur EPXA4 Devices Errata Sheet ■ 4 utilizes three extra logic elements in the device and adds minimal corresponding delay to the bridge timing. If logic element usage or bridge timing is critical to your design, you can disable the automatic Quartus II routing option by adding the following parameter to the defparam section of the stripe instantiation file generated by the ® ...
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... Ensure that the AHB1/2 clock frequency is less than or equal to 4 times the SDRAM clock frequency. Embedded EPXA4 devices include the ARM ETM9 version 2a. Please see the ETM9_Rev_2a_Errata.doc for errata on this version of the ETM9. This Trace Module document is available on the ARM Limited website. ...
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... This section provides further information about errata in configuration. 7.1 JTAG Configuration Error JTAG configuration of the EPXA4 does not complete successfully if there are programmed EPC configuration devices in the JTAG chain and the EPXA4 is in boot-from-serial mode. The Quartus II Programmer reports an error stating that the CONF_DONE signal did not go high. ...
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This appendix reproduces information supplied by ARM Ltd. on known errata in the ARM922T little or no impact on the use of the Excalibur device, but could be useful, on rare occasions, in understanding its interaction with third-party debugging tools. ...
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A.1 Errata for the ARM920T AHB Wrapper Module This section documents errata in the ARM920T AHB wrapper module, which is used in the Excalibur device. A.1.1 Linefill Counter—Category 2 The burst counter for a cache linefill is incorrectly pre-loaded if ...
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A.2 Errata for the ETM9 Trace Module See Table 1 on page 7 and associated text for an explanation of categorisation. A.2.1 Invalid data trace following FIFO overflow—Category 1 Note: ARM has updated the errata classifications. This is a category ...
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Table 2. Example of invalid data trace following overflow during wait-state period Address Instruction Data trace entering ETM FIFO 1004 LDMIA r6, {r0 – r4} [r6] [r6+1] [r6+2] [r6+3] [r6+4] 1008 LDR r7, [r8] [r8] Notes: (a) Corresponds to data ...
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Conditions Extended wait-state periods can be caused by cache misses in cached systems, or the use of a slow memory system. Consequently, the problem is unlikely to occur in uncached systems or in systems where the speed of the memory ...
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Table 3. Minimum length of the wait-state period for the problem to occur ETM Configuration FIFO size Large 45 bytes Medium 18 bytes Small 9 bytes While the minimum number of consecutive wait states required for this erratum to occur ...
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Implications While instruction trace remains unaffected, the user is unable to ascertain whether the data trace is correct. The erratum must be considered when the following occur together: ■ ■ ■ ■ ■ Altera Corporation An overflow is reported. The ...
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One of the following apply: The first instruction traced following the overflow is an indirect branch. The next instruction to have data traced does not occur until after the next indirect branch. Other instructions have data traced before the next ...
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Workaround This workaround is for tool vendors only and must be read in conjunction with the Embedded Trace Macrocell Specification (ARM IHI 0014). Development tool vendors can implement the above checks automatically in the trace tools, so that all data ...
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A.2.2 Execution status unknown prior to an interrupt or prefetch abort—Category 2 Description The trace port protocol allows for each instruction traced to be reported with a corresponding branch address to indicate the address of the next instruction. If this ...
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Table 4 Table 5 Table 4. Example of incorrect trace behavior on interrupt Actual instructions executed Address Instruction 0x00001000 ADD r1, r1, 1 0x00001004 B 0x00001020 (0x00001020) (Not executed due to interrupt) IRQ hander 0x00000018 . . . . . ...
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Conditions The conditions under which this erratum occurs are not easily predicted. It never occurs if the last executed instruction failed its condition codes. Implications The last instruction executed before an interrupt or prefetch abort might be missing from the ...
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A.2.3 Instruction displayed before and after overflow—Category 2 Description When the FIFO overflows, the last instruction to be traced immediately before overflow may be repeated on recovery from overflow. Conditions The instruction must be executing when the overflow occurs and ...
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A.2.4 Address range cannot include 0xFFFFFFFF—Category 2 Description There is no way to define a range which includes 0xFFFFFFFF . Ranges are defined to be exclusive of the upper address range with an upper address of 0xFFFFFFFF only ...
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Conditions This occurs when both of the following are true: ■ ■ Implications Extra CPRT data is traced. Since the number of such transfers is relatively small, the amount of extra data generated should not be significant. As there is ...
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It is occasionally useful to be able to determine the exact cycles on which instructions are executed, for example to perform basic performance analysis or to diagnose problems with the memory system. The information can be preserved by one of ...
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Table 6. Example of correct and incorrect trace in the presence of stalls (Part 511 (Branch delay) 512 (Branch delay) 513 1040 NOP 514 515 516 517 518 519 520 521 522 Conditions As shown in CLKEN ...
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It is therefore possible to determine where external stall cycles have been inserted, and to count forward 6 cycles from that point to find where they should have been inserted, not counting other external stall cycles. This is a complex ...
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Table 7. Example of how to calculate the correct location of a stall (Part 618 619 620 621 Note: If 2018 is also an LDR, rather than an ADD, then it would not be possible to determine ...
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A.2.8 Extra instruction traced prior to debug entry—Category 3 Description An instruction selected as a breakpoint may be traced prior to debug entry, even though it was not executed flagged as having failed its condition codes, regardless of ...
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A.3 Errata for the ARM922T Processor Core A.3.1 LDM of user mode registers (ARM9TDMI–8)—Category 2 ARM9 Bug tracking database entry : CPC00_CAM_000013 Summary Under specific conditions, a LDM to user mode registers will not operate correctly. These instructions take the ...
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Notes: In all privileged modes this errata exists if the base register greater. This is not restricted to FIQ mode. Instructions of the form operate correctly since these are not LDM to user mode register instructions. These ...
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The instruction: should be split into and should be split into A.3.2 Debug Request coincident with Pipeline Hazards (ARM9TDMI–9) —Category 2 Summary The processor may return to normal program execution at an incorrect point if EDBGRQ or the scan ...
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If the above conditions are met then the debug entry mechanism fails to behave in the defined manner and the device may return from debug and execute from an incorrect address. Implications For each scenario the following implications are ...
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Workarounds There is no practical workaround for this erratum. This is due to the difficulty in getting a debugging tool to recognise the symptoms of this erratum and take the appropriate corrective action. However the likelihood of failure with this ...
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Workarounds There is no practical workaround for this erratum. This is due to the difficulty in getting a debugging tool to recognise the symptoms of this erratum and take the appropriate corrective action. However the likelihood of failure with this ...
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A.3.5 Register controlled shift data operations where the destination is the PC (ARM9TDMI–1)—Category 3 ARM9 Bug tracking database entry : CPC00_CAM_000001 Summary A data operation with a register controlled shift to the PC may calculate an incorrect result Description This ...
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Examples: The only theoretical use for these instructions which has been suggested would be for a branch table that was organised in powers date ARM knows of no examples of an application for a branch table organised ...