DM74LS503N Fairchild Semiconductor, DM74LS503N Datasheet
DM74LS503N
Manufacturer Part Number
DM74LS503N
Description
IC REGISTER W/EXP CONT 16-DIP
Manufacturer
Fairchild Semiconductor
Series
74LSr
Datasheet
1.DM74LS503N.pdf
(4 pages)
Specifications of DM74LS503N
Logic Type
Register, Successive Approximation
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Function
Universal
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LS503
© 2000 Fairchild Semiconductor Corporation
DM74LS503N
DM74LS503
8-Bit Successive Approximation Register
(with Expansion Control)
General Description
The DM74LS503 register has an active LOW Enable (E)
input that is used in cascading two or more packages for
longer word lengths. A HIGH signal on E, after a START
operation, forces Q7 HIGH and prevents the device from
accepting serial data. With the E input of an DM74LS503
connected to the CC output of a preceding (more signifi-
cant) device, the DM74LS503 will be inhibited until the pre-
ceding device is filled, causing its CC output to go LOW.
This LOW signal then enables the DM74LS503 to accept
the serial data on subsequent clocks.
Ordering Code:
Connection Diagram
Pin Descriptions
Order Number
Package Number
N16E
D
S
CP
E
CC
Q0–Q7
Q7
Pin Names
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS010190
Serial Data Input
Start Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Conversion Enable Input (Active LOW)
Conversion Complete Output (Active LOW)
Parallel Register Outputs
Complement of Q7 Output
Features
Logic Symbol
V
GND
Description
CC
Performs serial-to-parallel conversion
Expansion control for longer words
Storage and control for successive approximation A to D
conversion
Low power Schottky version of 2503
Pin 16
Pin 8
Package Description
March 1989
Revised March 2000
www.fairchildsemi.com
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DM74LS503N Summary of contents
Page 1
... CC output to go LOW. This LOW signal then enables the DM74LS503 to accept the serial data on subsequent clocks. Ordering Code: Order Number Package Number DM74LS503N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Pin Descriptions Pin Names ...
Page 2
Logic Diagrams Note: Cell logic is repeated for register stages Q5 to Q1. Connection for Longer Word Lengths www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...