74ACT299SCX Fairchild Semiconductor, 74ACT299SCX Datasheet - Page 2

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74ACT299SCX

Manufacturer Part Number
74ACT299SCX
Description
IC SHIFT/REGISTER STORE 20SOIC
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Datasheet

Specifications of 74ACT299SCX

Logic Type
Shift Register
Output Type
Standard
Number Of Elements
1
Number Of Bits Per Element
8
Function
Universal
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ACT299SCX
Manufacturer:
FSX
Quantity:
20 000
www.fairchildsemi.com
Logic Symbols
IEEE/IEC
2
Truth Table
H
L

X
Functional Description
The AC/ACT299 contains eight edge-triggered D-type flip-
flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S
shown in the Truth Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi-
ated by the rising edge of the clock. Inputs can change
when the clock is in either state provided only that the rec-
ommended setup and hold times, relative to the rising edge
of CP, are observed.
A HIGH signal on either OE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, hold, load and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
lel load operation.
MR S
H
H
H
H
L
LOW Voltage Level
HIGH Voltage Level
Immaterial
LOW-to-HIGH Transition
Inputs
H
H
X
L
L
1
S
X
H
H
L
L
0
CP



X
X
Asynchronous Reset; Q
Parallel Load; I/O
Shift Right; DS
Shift Left, DS
Hold
0
and S
1
or OE
1
in preparation for a paral-
Response
7
2
0
disables the 3-STATE
n
Q
Q
7
, Q
0
Q
, Q
7
n
0
0
–Q
0
and S
0
7
Q
and Q
Q
6
, etc.
LOW
1
, etc.
1
, as
7

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