74VHC123AM Fairchild Semiconductor, 74VHC123AM Datasheet - Page 5

• Manufacturer Part Number: 74VHC123AM
• Description: IC MULTIVIBRATOR MONO DL 16-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr

Specifications of 74VHC123AM

• Logic Type: Monostable
• Independent Circuits: 2
• Schmitt Trigger Input: No
• Propagation Delay: 8.1ns
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Elements Per Chip: 2
• Logic Family: VHC
• Input Bias Current (max): 0.004 mA
• Propagation Delay Time: 24.1 ns, 14 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Multivibrator Type: Dual Retriggerable Monostable
• Output Current: 8mA
• Logic Case Style: SOIC
• No. Of Pins: 16
• Supply Voltage Range: 2V To 5.5V
• Rohs Compliant: Yes
• Dc: 0052
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1993 Fairchild Semiconductor Corporation
74VHC123A Rev. 1.2
Functional Description
1. Stand-by State
2. Trigger Operation
The external capacitor (C
the Stand-by State. That means, before triggering,
the Q
R
relate to the timing of the output pulse, and two refer-
ence voltage supplies turn off. The total supply cur-
rent is only leakage current.
Trigger operation is effective in any of the following
three cases. First, the condition where the A input is
LOW, and B input has a rising signal; second, where
the B input is HIGH, and the A input has a falling sig-
nal; and third, where the A input is LOW and the B
input is HIGH, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C
and C
external capacitor discharges through Q
age level at the R
age level falls to the internal reference voltage V
the output of C
reset and Q
C
After Q
starts rising at a rate determined by the time constant
of external capacitor C
Upon triggering, output Q becomes HIGH, following
some delay time of the internal F/F and gates. It stays
HIGH even if the voltage of R
ing to rising. When R
ence voltage V
x
2
/C
continues operating.
x
P
node are in the off state. Two comparators that
2
and Q
N
start operating, and Q
turns off, the voltage at the R
N
N
turns off. At that moment C
transistors which are connected to the
ref
1
becomes LOW. The flip-flop is then
H, the output of C
x
/C
x
x
x
/C
node drops. If the R
and resistor R
x
x
) is fully charged to V
reaches the internal refer-
x
/C
N
x
is turned on. The
changes from fall-
2
becomes LOW,
x
.
N
1
x
. The volt-
/C
stops but
x
/C
x
x
node
CC
volt-
ref
L,
in
1
5
3. Retrigger operation (74VHC123A)
4. Reset Operation
the output Q goes LOW and C
That means, after triggering, when the voltage level
of the R
MONOSTABLE state.
With large values of C
charge time of the capacitor and internal delays of
the IC, the width of the output pulse, t
follows:
t
When a new trigger is applied to either input A or B
while in the MONOSTABLE state, it is effective only if
the IC is charging C
node then falls to V
output stays HIGH if the next trigger comes in before
the time period set by C
If the new trigger is very close to a previous trigger,
such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2nd
trigger, t
In normal operation, the CLR input is held HIGH. If
CLR is LOW, a trigger has no affect because the Q
output is held LOW and the trigger control F/F is
reset. Also, Q
V
This means if CLR is set LOW, the IC goes into a wait
state.
W
CC
(OUT)
.
x
RR
/C
x
(Min), depends on V
1.0 C
node reaches V
p
turns on and C
x
R
ref
x
x
. The voltage level of the R
L level again. Therefore the Q
x
x
and R
and R
ref
x
H, the IC returns to its
x
, and ignoring the dis-
x
2
CC
.
is charged rapidly to
stops its operation.
and C
W
www.fairchildsemi.com
(OUT), is as
x
.
x
/C
x