CD4538BCM Fairchild Semiconductor, CD4538BCM Datasheet - Page 3

• Manufacturer Part Number: CD4538BCM
• Description: IC MULTIVIBRATOR DUAL 16-SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 4000Br

Specifications of CD4538BCM

• Logic Type: Monostable
• Independent Circuits: 2
• Schmitt Trigger Input: No
• Propagation Delay: 100ns
• Current - Output High, Low: 8.8mA, 8.8mA
• Voltage - Supply: 3 V ~ 15 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Elements Per Chip: 2
• Logic Family: CD4000
• Input Bias Current (max): 0.02 mA
• Propagation Delay Time: 600 ns, 300 ns, 220 ns
• High Level Output Current: - 4.2 mA
• Low Level Output Current: 4.2 mA
• Supply Voltage (max): 15 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V, 9 V, 12 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
Trigger Operation
The block diagram of the CD4538BC is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and Figure 2, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor C
to V
(while inputs B and C
recognized, which turns on comparator C1 and N-Channel
transistor N1
With transistor N1 on, the capacitor C
toward V
of comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time com-
parator C2 turns on. With transistor N1 off, the capacitor C
begins to charge through the timing resistor, R
V
tor C2 changes state causing the output latch to reset (Q
goes low) while at the same time disabling comparator C2.
This ends the timing cycle with the monostable in the qui-
escent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from V
V
It should be noted that in the quiescent state C
charged to V
be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the CD4538BC is that the output latch is set via
the input trigger without regard to the capacitor voltage.
DD
DD
. When the voltage across C
)
DD
(2)
DD
. When the trigger input A goes from V
.
SS
to V
until V
DD
(1)
SS
. At the same time the output latch is set.
, causing the current through resistor R
(while input A is at V
REF1
D
is reached. At this point the output
are held to V
X
equals V
X
SS
DD
X
completely charged
rapidly discharges
) a valid trigger is
and input C
REF2
, compara-
SS
X
X
, toward
to V
is fully
D
is at
X
FIGURE 2.
DD
to
X
3
Thus, propagation delay from trigger to Q is independent of
the value of C
form.
Retrigger Operation
The CD4538BC is retriggered if a valid trigger occurs
lowed by another valid trigger
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin 2 or 14 has begun to rise
from V
increase in output pulse width T. When a valid retrigger is
initiated
progressing along the RC charging curve toward V
Q output will remain high until time T, after the last valid
retrigger.
Reset Operation
The CD4538BC may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on C
fast charged to V
the voltage on the capacitor reaches V
will clear and then be ready to accept another pulse. If the
C
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the C
made significantly shorter than the minimum pulse width
specification.
D
input is held low, any trigger inputs that occur will be
D
REF1
sets the reset latch and causes the capacitor to be
(4)
, the voltage at T2 will again drop to V
, but has not yet reached V
X
, R
DD
X
, or the duty cycle of the input wave-
by turning on transistor Q1
D
input, the output pulse T can be
(4)
before the Q output has
REF2
REF2
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, the reset latch
, will cause an
REF1
(5)
DD
. When
before
(3)
. The
fol-