CY7C130-45DMB Cypress Semiconductor Corporation., CY7C130-45DMB Datasheet

CY7C130-45DMB

Manufacturer Part Number

CY7C130-45DMB

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C141-55JC.pdf (19 pages)

2.CY7C141-55JC.pdf (16 pages)

3.CY7C141-55JC.pdf (16 pages)

Specifications of CY7C130-45DMB

Date_code

00+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C130-45DMB

Manufacturer:

CYP

Quantity:

307

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Features

Notes:

Logic Block Diagram

Cypress Semiconductor Corporation

• True Dual-Ported memory cells which allow simulta-

• 1K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: I

• Fully asynchronous operation

• Automatic power-down

• Master CY7C130/CY7C131 easily expands data bus

• BUSY output flag on CY7C130/CY7C131; BUSY input

• INT flag for port-to-port communication

• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and

• Pin-compatible and functionally equivalent to

neous reads of the same memory location

width to 16 or more bits using slave CY7C140/CY7C141

on CY7C140/CY7C141

52-pin TQFP

IDT7130/IDT7140

CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor

CY7C140/CY7C141 (Slave): BUSY is input.

Open drain outputs: pull-up resistor required

BUSY

INT

R/W

I/O

[1]

[2]

DECODER

ADDRESS

R/W

= 90 mA (max.)

CONTROL

I/O

(7C130/7C131 ONLY)

INTERRUPT LOGIC

ARBITRATION

•

MEMORY

ARRAY

LOGIC

AND

3901 North First Street

CONTROL

I/O

DECODER

ADDRESS

R/W

Functional Description

The

high-speed CMOS 1K by 8 dual-port static RAMs. Two ports

are provided permitting independent access to any location in

memory. The CY7C130/ CY7C131 can be utilized as either a

standalone 8-bit dual-port static RAM or as a master dual-port

RAM in conjunction with the CY7C140/CY7C141 slave du-

al-port device in systems requiring 16-bit or greater word

widths. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or

multiprocessor designs.

Each port has independent control pins; chip enable (CE),

write enable (R/W), and output enable (OE). Two flags are

provided on each port, BUSY and INT. BUSY signals that the

port is trying to access the same location currently being ac-

cessed by the other port. INT is an interrupt flag indicating that

data has been placed in a unique location (3FF for the left port

and 3FE for the right port). An automatic power-down feature

is controlled independently on each port by the chip enable

(CE) pins.

The CY7C130 and CY7C140 are available in 48-pin DIP. The

CY7C131 and CY7C141 are available in 52-pin PLCC and

PQFP.

1K x 8 Dual-Port Static Ram

CY7C130/CY7C131/CY7C140

•

San Jose

INT

R/W

I/O

BUSY

C130-1

[2]

May 1989 – Revised March 27, 1997

•

CY7C130/CY7C131

CY7C140/CY7C141

CA 95134

BUSY

R/W

Pin Configurations

I/O

INT

GND

Top View

and

7C130

7C140

DIP

•

fax id: 5200

CY7C141

408-943-2600

R/W

INT

I/O

BUSY

C130-2

are

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