AM27C512-90DC Advanced Micro Devices, AM27C512-90DC Datasheet

AM27C512-90DC

Manufacturer Part Number

AM27C512-90DC

Description

Manufacturer

Advanced Micro Devices

Datasheet

1.AM27C512-90DC.pdf (12 pages)

Specifications of AM27C512-90DC

Case

DIP/28

Date_code

95+

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Am27C512

512 Kilobit (64 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

The Am27C512 is a 512-Kbit, ultraviolet erasable pro-

grammable read-only memory. It is organized as 64K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast

single address location programming. Products are

available in windowed ceramic DIP packages, as well

as plastic one time programmable (OTP) PDIP and

PLCC packages.

Data can be typically accessed in less than 55 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

BLOCK DIAGRAM

Fast access time

— Speed options as fast as 55 ns

Low power consumption

— 20 µA typical CMOS standby current

JEDEC-approved pinout

Single +5 V power supply

100% Flashrite™ programming

— Typical programming time of 8 seconds

10% power supply tolerance standard

FINAL

A0–A15

Address

Inputs

OE#/V

CE#

Output Enable

Chip Enable

Prog Logic

Decoder

and

thus eliminating bus contention in a multiple bus micro-

processor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 80 mW in active mode, and

100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses), re-

sulting in a typical programming time of 8 seconds.

Latch-up protected to 100 mA from –1 V to

High noise immunity

Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

Standard 28-pin DIP, PDIP, and 32-pin PLCC

packages

+ 1 V

Data Outputs

DQ0–DQ7

524,288

Buffers

Bit Cell

Output

Gating

Matrix

Publication# 08140

Issue Date: May 1998

Rev: I Amendment/0

08140I-1

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