MC74ACT573DWR2G ON Semiconductor, MC74ACT573DWR2G Datasheet - Page 2

• Manufacturer Part Number: MC74ACT573DWR2G
• Description: IC BUFF DVR TRI-ST OCTAL 20SOIC
• Manufacturer: ON Semiconductor
• Series: 74ACTr
• Type: D-Typer

Specifications of MC74ACT573DWR2G

• Logic Type: D-Type Latch
• Circuit: 1:8
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 10ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: ACT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Polarity: Non-Inverting
• Technology: CMOS
• Package Type: SOIC W
• Propagation Delay Time: 12ns
• Operating Supply Voltage (typ): 5V
• High Level Output Current: -24mA
• Low Level Output Current: 24mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74ACT573DWR2GOS

TRUTH TABLE
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
LE
OE
= Previous O
OE
H
L
L
L
D
0
D
0
before LOW−to−HIGH Transition of Clock
LE
Inputs
LE
Q
H
H
X
L
O
D
0
1
NOTE:
D
LE
Q
D
That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
H
L
X
X
n
O
D
1
2
D
MC74AC573, MC74ACT573
LE
Q
Outputs
Figure 3. Logic Diagram
O
O
H
O
L
Z
D
n
0
2
http://onsemi.com
3
D
LE
Q
2
O
D
Functional Description
latches with 3−state output buffers. When the Latch Enable
(LE) input is HIGH, data on the D
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
enabled. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
3
4
The MC74AC573/74ACT574 contains eight D−type
D
LE
Q
O
D
4
5
D
LE
Q
O
D
5
6
D
LE
n
Q
inputs enters the latches.
O
D
7
6
D
LE
Q
O
7