74VCX162373MTDX Fairchild Semiconductor, 74VCX162373MTDX Datasheet

74VCX162373MTDX

Manufacturer Part Number

74VCX162373MTDX

Description

IC LATCH TRANSP 16BIT LV 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXr

Datasheet

1.74VCX162373MTD.pdf (8 pages)

Specifications of 74VCX162373MTDX

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

1.4 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1ns

Current - Output High, Low

12mA, 12mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74VCX162373MTD

74VCX162373

Low Voltage 16-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs

and 26: Series Resistors in Outputs

General Description

The VCX162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

The VCX162373 is also designed with 26

outputs. This design reduces line noise in applications

such as memory address drivers, clock drivers and bus

transceivers/transmitters.

The 74VCX162373 is designed for low voltage (1.4V to

3.6V) V

The 74VCX162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Ordering Number

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

applications with I/O compatibility up to 3.6V.

Package

Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

resistors in the

DS500236

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

1.4V–3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Support live insertion and withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

Pin Names

3.3 ns max for 3.0V to 3.6V V

Human body model

Machine model

12 mA @ 3.0V V

series resistors in outputs

Package Description

–I

–O

to O

)

Output Enable Input (Active LOW)

Latch Enable Input

Inputs

Outputs

supply operation

)

200V

2000V

through a pull-up resistor; the minimum

January 2000

Revised June 2005

Description

www.fairchildsemi.com

Related parts for 74VCX162373MTDX

74VCX162373MTDX Summary of contents

Page 1

... MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation Features 1.4V–3.6V V supply operation CC 3.6V tolerant inputs and outputs ...

Page 2

Connection Diagram Functional Description The 74VCX162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current Increase in I per Input CC CC ...

Page 5

AC Electrical Characteristics Symbol Parameter t Pulse Width Output to Output Skew C OSHL L t (Note 7) OSLH C L Note 6: For add approximately 300 ps to the AC ...

Page 6

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 8. Waveform for Inverting and FIGURE 9. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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