ZL30111QDG1 Zarlink Semiconductor, ZL30111QDG1 Datasheet

ZL30111QDG1

Manufacturer Part Number

ZL30111QDG1

Description

Manufacturer

Zarlink Semiconductor

Datasheets

1.ZL30111.pdf (21 pages)

2.ZL30111QDG1.pdf (20 pages)

Specifications of ZL30111QDG1

Lead_time

2 weeks

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Features

•

Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or

19.44 MHz input

Provides a range of clock outputs: 2.048 MHz,

4.096 MHz and 8.192 MHz

Provides 2 styles of 8 kHz framing pulses

Automatic entry and exit from freerun mode on

reference fail

Provides DPLL lock and reference fail indication

DPLL bandwidth of 922 Hz for all rates of input

reference and 58 Hz for an 8 kHz input reference

Less than 0.6 ns

20 MHz external master clock source: clock

oscillator or crystal

Simple hardware control interface

OSCo

OSCi

RST

REF

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

intrinsic jitter on all output clocks

Reference

State Machine

Monitor

Master

Clock

Figure 1 - Functional Block Diagram

Control

Mode

Zarlink Semiconductor Inc.

REF_FAIL

DPLL

Applications

•

Description

The ZL30111 POTS line card PLL contains a digital

phase-locked loop (DPLL), which provides timing and

synchronization for SLIC/CODEC devices.

The ZL30111 generates TDM clock and framing

signals that are phase locked to the input reference.

It helps ensure system reliability by monitoring its

reference for stability and by maintaining stable

output clocks during short periods when the

reference is unavailable.

ZL30111QDG

ZL30111QDG1

Synchronizer for POTS line cards

Rate convert NTR 8kHz or GPON physical

interface clock to TDM clock

LOCK

Ordering Information

64 Pin TQFP

64 Pin TQFP* Trays, Bake & Drypack

*Pb Free Matte Tin

-40°C to +85°C

POTS Line Card PLL

Trays, Bake & Drypack

Data Sheet

ZL30111

C2o

January 2007

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