CY7C1360C-200BZC Cypress Semiconductor Corporation., CY7C1360C-200BZC Datasheet

CY7C1360C-200BZC

Manufacturer Part Number

CY7C1360C-200BZC

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1360C-200BZC.pdf (31 pages)

2.CY7C1360C-200BZC.pdf (31 pages)

3.CY7C1360C-200BZC.pdf (31 pages)

Specifications of CY7C1360C-200BZC

Package

QFP

Date_code

09+

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Cypress Semiconductor Corporation

Document #: 38-05540 Rev. *H

Features

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply (V

• 2.5V/3.3V I/O operation (V

• Fast clock-to-output times

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Available in lead-free 100-Pin TQFP package, lead-free

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• IEEE 1149.1 JTAG-Compatible Boundary Scan

A0, A1, A

Logic Block Diagram – CY7C1362C (512K x 18)

— 2.8 ns (for 250-MHz device)

Pentium

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

MODE

ADSC

ADSP

ADV

BWE

CLK

CE2

CE3

is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

interleaved or linear burst sequences

WRITE REGISTER

CONTROL

SLEEP

ADDRESS

ENABLE

DQP

DDQ

)

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

COUNTER AND

CLR

BURST

LOGIC

PIPELINED

ENABLE

•

A[1:0]

198 Champion Court

WRITE DRIVER

DQP

Functional Description

The CY7C1360C/CY7C1362C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE

Enables (CE

and ADV), Write Enables (BW

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW cause s all bytes to be written.

The CY7C1360C/CY7C1362C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

•

MEMORY

ARRAY

San Jose

and CE

SENSE

AMPS

CA 95134-1709

[2]

), Burst Control inputs (ADSC, ADSP,

REGISTERS

OUTPUT

[1]

, and BWE), and Global Write

Revised September 14, 2006

), depth-expansion Chip

BUFFERS

OUTPUT

CY7C1360C

CY7C1362C

•

REGISTERS

408-943-2600

INPUT

DQs

DQP

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