74AUP1G885GT,115 NXP Semiconductors, 74AUP1G885GT,115 Datasheet

IC GATE DUAL FUNCTION 8-XSON

74AUP1G885GT,115

Manufacturer Part Number
74AUP1G885GT,115
Description
IC GATE DUAL FUNCTION 8-XSON
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP1G885GT,115

Logic Type
Configurable Multiple Function
Number Of Circuits
1
Number Of Inputs
3
Schmitt Trigger Input
Yes
Output Type
Single-Ended
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-XSON
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4389-2
74AUP1G885GT-G
74AUP1G885GT-G
935280767115
1. General description
2. Features and benefits
The 74AUP1G885 provides two functions in one device. The output state of the outputs
(1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean
function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
CC
74AUP1G885
Low-power dual function gate
Rev. 6 — 21 October 2010
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
OFF
range from 0.8 V to 3.6 V.
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial Power-down mode operation
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 μA (maximum)
CC
Product data sheet
OFF
. The I
OFF

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74AUP1G885GT,115 Summary of contents

Page 1

Low-power dual function gate Rev. 6 — 21 October 2010 1. General description The 74AUP1G885 provides two functions in one device. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1G885DC −40 °C to +125 °C 74AUP1G885GT −40 °C to +125 °C 74AUP1G885GF −40 °C to +125 °C 74AUP1G885GD −40 °C to +125 °C 74AUP1G885GM −40 °C to +125 °C 74AUP1G885GN − ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G885 GND 001aae354 Fig 2. Pin configuration SOT765-1 74AUP1G885 GND 4 Transparent top view Fig 4. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 GND 4 n. 74AUP1G885 ...

Page 4

... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC C input capacitance ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC = −40 °C to +125 °C ...

Page 8

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off OFF leakage current I supply current CC ΔI additional supply current CC − 0.6 V, other inputs at V ...

Page 9

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions propagation delay 1Y; see 2Y; see propagation delay 1Y; see 2Y; see 74AUP1G885 Product data sheet Figure [2] Figure [2] Figure ...

Page 10

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions propagation delay 1Y; see 2Y; see propagation delay 1Y; see 2Y; see 74AUP1G885 Product data sheet …continued Figure [2] Figure [2] Figure ...

Page 11

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V [ the same as t and PLH PHL [3] All specified values are the average typical values over all stated loads. ...

Page 12

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for measuring switching times Table 10. ...

Page 13

... NXP Semiconductors 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 16

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 11. Package outline SOT996-2 (XSON8U) ...

Page 17

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 19

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 20

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date 74AUP1G885 v.6 20101021 • Modifications: Added type number 74AUP1G885GF (SOT1089/XSON8 package). ...

Page 21

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 22

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1G885 Product data sheet 16 ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline ...

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