ISPLSI1048EA125LT128 Lattice Semiconductor Corp., ISPLSI1048EA125LT128 Datasheet

ISPLSI1048EA125LT128

Manufacturer Part Number

ISPLSI1048EA125LT128

Description

TQFP

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI1048EA125LT128.pdf (14 pages)

Specifications of ISPLSI1048EA125LT128

Date_code

05+

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• HIGH DENSITY PROGRAMMABLE LOGIC

• NEW FEATURES

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1048ea_04

Features

— 8,000 PLD Gates

— 96 I/O Pins, Eight Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Functionally Compatible with ispLSI 1048C and 1048E

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable Via IEEE 1149.1

— User Selectable 3.3V or 5V I/O supports Mixed

— Open Drain Output Option

—

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Machines, Address Decoders, etc.

(JTAG) Test Access Port

Voltage Systems (V

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 170 MHz Maximum Operating Frequency

pd = 5.0 ns Propagation Delay

CCIO

CMOS

Pin)

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1048EA is a High Density Programmable

Logic Device containing 288 Registers, 96 Universal I/O

pins, eight Dedicated Input pins, four Dedicated Clock

Input pins, two dedicated Global OE input pins, and a

Global Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 1048EA features 5V in-system programmability

and in-system diagnostic capabilities via IEEE 1149.1

Test Access Port. The ispLSI 1048EA offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect to provide truly reconfigurable systems. A functional

superset of the ispLSI 1048 architecture, the ispLSI

1048EA device adds user selectable 3.3V or 5V I/O and

open-drain output options.

The basic unit of logic on the ispLSI 1048EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7 (see Figure 1). There are a total of 48 GLBs in the

ispLSI 1048EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and dedicated inputs. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

Functional Block Diagram

Description

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Logic

Array

Output Routing Pool

1048EA

D Q

GLB

January 2002

0139A/1048EA

CLK

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