ISPLSI104850LQI Lattice Semiconductor Corp., ISPLSI104850LQI Datasheet

ISPLSI104850LQI

Manufacturer Part Number

ISPLSI104850LQI

Description

QFP

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI104850LQI.pdf (12 pages)

Specifications of ISPLSI104850LQI

Date_code

04+

Current page: 1 of 12
Download datasheet (121Kb)

• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• COMBINES EASE OF USE AND THE FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1048_06

Features

— 8000 PLD Gates

— 96 I/O Pins, Ten Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Security Cell Prevents Unauthorized Copying

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E

— 100% Tested

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

SPEED OF PLDs WITH THE DENSITY AND FLEX-

— Complete Programmable Device Can Combine Glue

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

Market, and Improved Product Quality

Machines, Address Decoders, etc.

Logic and Structured Designs

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 80 MHz Maximum Operating Frequency

max = 50 MHz for Industrial Devices

pd = 15 ns Propagation Delay

CMOS Technology

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1048 is a High-Density Programmable Logic

Device which contain 288 Registers, 96 Universal I/O

pins, ten Dedicated Input pins, four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1048 features 5-Volt in-system

programming and in-system diagnostic capabilities. It is

the first device which offers non-volatile reprogrammability

of the logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 1048 devices is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. F7 (see figure 1). There are a total of 48 GLBs in the

ispLSI 1048 device. Each GLB has 18 inputs, a program-

mable AND/OR/XOR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

other GLB on the device.

Functional Block Diagram

Description

F7 F6 F5 F4 F3 F2 F1 F0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

E7 E6 E5 E4 E3 E2 E1 E0

C0 C1 C2 C3 C4 C5 C6 C7

Logic

Array

Output Routing Pool

D Q

GLB

1048

August 2000

CLK

Related parts for ISPLSI104850LQI

Related keywords

ISPLSI104850LQI datasheet
ISPLSI104850LQI data sheet
ISPLSI104850LQI pdf datasheet
ISPLSI104850LQI component
ISPLSI104850LQI part
ISPLSI104850LQI distributor
ISPLSI104850LQI RoHS
ISPLSI104850LQI datasheet download