ISPLSI102460LJ Lattice Semiconductor Corp., ISPLSI102460LJ Datasheet

ISPLSI102460LJ

Manufacturer Part Number

ISPLSI102460LJ

Description

PLCC-68

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI102460LJ.pdf (13 pages)

Specifications of ISPLSI102460LJ

Date_code

04+

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• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• COMBINES EASE OF USE AND THE FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1024_06

Features

— High-Speed Global Interconnect

— 4000 PLD Gates

— 48 I/O Pins, Six Dedicated Inputs

— 144 Registers

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Fast Random Logic

— Security Cell Prevents Unauthorized Copying

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E

— 100% Tested

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

SPEED OF PLDs WITH THE DENSITY AND FLEX-

— Complete Programmable Device Can Combine Glue

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

Market, and Improved Product Quality

Machines, Address Decoders, etc.

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

Logic and Structured Designs

max = 90 MHz Maximum Operating Frequency

max = 60 MHz for Industrial and Military/883 Devices

pd = 12 ns Propagation Delay

CMOS Technology

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

unctional

The ispLSI 1024 is a High-Density Programmable Logic

Device containing 144 Registers, 48 Universal I/O pins,

six Dedicated Input pins, four Dedicated Clock Input pins

and a Global Routing Pool (GRP). The GRP provides

complete interconnectivity between all of these elements.

The ispLSI 1024 features 5-Volt in-system programma-

bility and in-system diagnostic capabilities. It is the first

device which offers non-volatile reprogrammability of the

logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 1024 device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. C7 (see figure 1). There are a total of 24 GLBs in the

ispLSI 1024 device. Each GLB has 18 inputs, a program-

mable AND/OR/XOR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

other GLB on the device.

Functional Block Diagram

Description

Block Diagram

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

Logic

Array

D Q

GLB

February 1999

1024

CLK

0139-A-isp

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