IS61WV51216BLL Integrated Silicon Solution, IS61WV51216BLL Datasheet

IS61WV51216BLL

Manufacturer Part Number

IS61WV51216BLL

Description

TSOP44

Manufacturer

Integrated Silicon Solution

Datasheets

1.IS64WV51216BLL-10CTA3.pdf (21 pages)

2.IS61WV51216BLL.pdf (20 pages)

Specifications of IS61WV51216BLL

Date_code

10+

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IS61WV51216ALL

IS61WV51216BLL

IS64WV51216BLL

512K x 16 HIGH-SPEED ASYNCHRONOUS

CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Silicon Solution, Inc. — www.issi.com

Rev. E

06/17/08

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FUNCTIONAL BLOCK DIAGRAM

FEATURES

• High-speed access times:

• High-performance, low-power CMOS process

• Multiple center power and ground pins for greater

• Easy memory expansion with CE and OE op-

• CE power-down

• Fully static operation: no clock or refresh

• TTL compatible inputs and outputs

• Single power supply

• Packages available:

• Industrial and Automotive Temperature Support

• Lead-free available

• Data control for upper and lower bytes

noise immunity

tions

required

speed = 20ns for V

speed = 10ns for V

speed = 8ns for V

– 48-ball miniBGA (9mm x 11mm)

– 44-pin TSOP (Type II)

8, 10, 20 ns

1.65V to 2.2V (IS61WV51216ALL)

2.4V to 3.6V (IS61/64WV51216BLL)

3.3V + 5%

1.65V to 2.2V

2.4V to 3.6V

Lower Byte

Upper Byte

I/O8-I/O15

I/O0-I/O7

A0-A18

VDD

GND

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

DESCRIPTION

The

are high-speed, 8M-bit static RAMs organized as 512K

words by 16 bits. It is fabricated using

ance CMOS technology. This highly reliable process coupled

with innovative circuit design techniques, yields high-perfor-

mance and low power consumption devices.

When CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs, CE and OE. The active LOW

Write Enable (WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (UB) and Lower

Byte (LB) access.

The device is packaged in the JEDEC standard 44-pin

TSOP Type II and 48-pin Mini BGA (9mm x 11mm).

MEMORY ARRAY

COLUMN I/O

ISSI

512K x 16

IS61WV51216ALL/BLL and IS64WV51216BLL

JUNE 2008

ISSI

's high-perform-

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