IS61C64B15J Integrated Silicon Solution, IS61C64B15J Datasheet

IS61C64B15J

Manufacturer Part Number

IS61C64B15J

Description

SOJ28

Manufacturer

Integrated Silicon Solution

Datasheet

1.IS61C64B15J.pdf (9 pages)

Specifications of IS61C64B15J

Date_code

04+

Current page: 1 of 9
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Integrated Silicon Solution, Inc. — www.issi.com —

Rev. D

07/01/02

IS61C64B

FEATURES

• High-speed access time: 10, 12, and 15 ns

• Automatic power-down when chip is

• CMOS low power operation

• TTL compatible interface levels

• Single 5V power supply

• Fully static operation: no clock or refresh

• Three state outputs

• One Chip Enables (CE) for increased speed

assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device

specification before relying on any published information and before placing orders for products.

8K x 8 HIGH-SPEED CMOS STATIC RAM

deselected

— 450 mW (typical) operating

— 250 µW (typical) standby

required

FUNCTIONAL BLOCK DIAGRAM

I/O0-I/O7

A0-A12

VCC

GND

DECODER

CIRCUIT

CONTROL

CIRCUIT

DATA

I/O

1-800-379-4774

DESCRIPTION

The

8192-word by 8-bit static RAM. It is fabricated using

performance CMOS technology. This highly reliable process

coupled with innovative circuit design techniques, yields ac-

cess times as fast as 10 ns with low power consumption.

When CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down to

250 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using one Chip Enable

input, CE. The active LOW Write Enable (WE) controls both

writing and reading of the memory.

The IS61C64B is packaged in the JEDEC standard 28-pin,

300-mil SOJ, and TSOP.

ISSI

IS61C64B is a very high-speed, low power,

MEMORY ARRAY

COLUMN I/O

256 X 256

ISSI

July 2002

ISSI

's high-

ISSI

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