74VCX16240MTD Fairchild Semiconductor, 74VCX16240MTD Datasheet

74VCX16240MTD

Manufacturer Part Number

74VCX16240MTD

Description

IC INVERTER DUAL 8-INPUT 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74VCXr

Datasheet

1.74VCX16240MTD.pdf (8 pages)

Specifications of 74VCX16240MTD

Logic Type

Inverter

Number Of Inputs

Number Of Circuits

Current - Output High, Low

24mA, 24mA

Voltage - Supply

1.2 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Logic Family

VCX

Number Of Channels Per Chip

Polarity

Inverting

Supply Voltage (max)

3.6 V

Supply Voltage (min)

1.2 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

High Level Output Current

- 24 mA

Low Level Output Current

24 mA

Minimum Operating Temperature

- 40 C

Number Of Lines (input / Output)

16 / 16

Output Type

3-State

Propagation Delay Time

6 ns at 1.8 V, 3 ns at 2.5 V, 2.5 ns at 3.3 V

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

74VCX16240MTDX

Manufacturer:

FAIRCHILD

Quantity:

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74VCX16240MTD

74VCX16240

Low Voltage 16-Bit Inverting Buffer/Line Driver with

3.6V Tolerant Inputs and Outputs

General Description

The VCX16240 contains sixteen inverting buffers with

3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74VCX16240 is designed for low voltage (1.2V to

3.6V) V

The 74VCX16240 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O capability up to 3.6V.

Package Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500099

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

1.2V to 3.6V V

3.6V tolerant inputs and outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

Pin Names

2.5 ns max for 3.0V to 3.6V V

Human body model

Machine model

24 mA @ 3.0V V

Package Descriptions

–I

–O

supply operation

Output Enable Input (Active LOW)

)

200V

2000V

through a pull-up resistor; the minimum

January 1998

Revised June 2005

Description

Outputs

Inputs

www.fairchildsemi.com

Related parts for 74VCX16240MTD

74VCX16240MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74VCX16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Functional Description The 74VCX16240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATED Outputs Active (Note 3) 0. Input Diode Current ( ...

Page 4

DC Electrical Characteristics Symbol Parameter V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ I Power-OFF Leakage Current OFF I Quiescent Supply Current Increase in I per Input CC CC ...

Page 5

AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t PLH t Output Enable Time PZL t PZH t Output Disable Time PLZ t PHZ t Output to Output Skew OSHL t (Note 7) OSLH Note 6: For C 50 ...

Page 6

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low ...

Page 7

AC Loading and Waveforms (V TEST PLH PHL PZL PLZ PZH PHZ FIGURE 6. Waveform for Inverting and Non-Inverting Functions FIGURE 7. 3-STATE Output High Enable and Disable Times for Low ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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