UCN5812F Allegro, UCN5812F Datasheet - Page 4

• Manufacturer Part Number: UCN5812F
• Description: BiMOS II 20-BIT SERIAL-INPUT / LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
• Manufacturer: Allegro

A. Minimum Data Active Time Before Clock Pulse
B. Minimum Data Active Time After Clock Pulse
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial
L = Low Logic Level
Input
Data
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
H
X
L
BLANKING
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
STROBE
DATA IN
CLOCK
Clock
Input
OUT
N
°
Shift Register Contents
I
H
L
R
X
P
1
1
1
H = High Logic Level
A
I
R
R
R
X
P
2
C
2
1
1
2
B
I
R
R
R
X
P
3
3
2
2
3
D
E
… I
… R
… R
… R
… X
… P
N-1
N-1
N-2
N-2
N-1
F
G
I
R
R
R
X
P
N
N-1
N-1
N
N
X = Irrelevant
Output
Serial
Data
R
R
R
P
X
N-1
N-1
N
N
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
Strobe
Input
H
L
P = Present State R = Previous State
Dwg. No. 12,649A
I
R
P
X
1
1
1
Latch Contents
I
R
P
X
2
2
2
I
R
P
X
3
3
3
… I
… R
… P
… X
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
N-1
N-1
N-1
Serial Data present at the input is transferred
Information present at any register is trans-
When the BLANKING input is high, the
I
X
R
P
N
N
N
Blanking
H
L
I
P
L
1
1
Output Contents
I
P
L
2
2
I
P
L
3
3
… I
… P
… L
N-1
N1
I
P
L
N
N