K4D261638 Samsung, K4D261638 Datasheet - Page 5

• Manufacturer Part Number: K4D261638
• Description: 128Mbit GDDR SDRAM
• Manufacturer: Samsung

INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
K4D261638F
LDQS,UDQS
For any applications using the single ended clocking, apply V
DQ
V
LDM,UDM
CK, CK*1
BA
V
A
DDQ
NC/RFU
Symbol
0
DD
0
V
CKE
RAS
CAS
WE
CS
0
~ DQ
~ A
REF
, BA
/V
/V
SS
SSQ
11
1
15
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
Type
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS
corresponds to the data on DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on
DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
’
s and DM
- 5 -
REF
to CK pin.
’
s that are sampled on both edges of the DQS.
0
~ RA
11
, Column addresses : CA
Function
128M GDDR SDRAM
Rev. 1.2 (Jan. 2004)
0
~ CA
8
.