GAL20XV10B-10LJ Lattice Semiconductor, GAL20XV10B-10LJ Datasheet

GAL20XV10B-10LJ

Manufacturer Part Number

GAL20XV10B-10LJ

Description

High-Speed E2CMOS PLD Generic Array Logic

Manufacturer

Lattice Semiconductor

Datasheet

1.GAL20XV10B-10LJ.pdf (14 pages)

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• HIGH PERFORMANCE E

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

• ACTIVE PULL-UPS ON ALL PINS

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

20xv10_02

The GAL20XV10 combines a high performance CMOS process

with electrically erasable (E

the highest speed Exclusive-OR PLD available in the market. At

90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides

a substantial savings in power when compared to bipolar counter-

parts. E

times providing the ability to reprogram, reconfigure or test the de-

vices quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configu-

rations possible with the GAL20XV10 are the PAL

listed in the macrocell description section of this document. The

GAL20XV10 is capable of emulating these PAL architectures with

full function and parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

Features

Description

— 10 ns Maximum Propagation Delay

— Fmax = 100 MHz

— 7 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS

— 90mA Maximum Icc

— 75mA Typical Icc

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

— XOR Gate Capability on all Outputs

— Full Function and Parametric Compatibility with

— Registered or Combinatorial with Polarity

— High Speed Counters

— Graphics Processing

— Comparators

CELL TECHNOLOGY

PAL12L10, 20L10, 20X10, 20X8, 20X4

CMOS technology offers high speed (<100ms) erase

Advanced CMOS Technology

) floating gate technology to provide

CMOS

TECHNOLOGY

architectures

Functional Block Diagram

Pin Configuration

GAL20XV10

I/CLK

I/OE

Top View

PLCC

I/O/Q

High-Speed E

GAL20XV10

Generic Array Logic™

I/CLK

GND

OLMC

20XV10

GAL

DIP

CMOS PLD

July 1997

I/O/Q

Vcc

I/O/Q

I/OE

I/O/Q

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