GAL20VP8B-15LJ Lattice Semiconductor, GAL20VP8B-15LJ Datasheet - Page 14

• Manufacturer Part Number: GAL20VP8B-15LJ
• Description: High-Speed E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

An electronic signature word is provided in every GAL20VP8 de-
vice. It contains 64 bits of reprogrammable memory that can contain
user defined data. Some uses include user ID codes, revision num-
bers, or inventory control. The signature data is always available
to the user independent of the state of the security cell.
NOTE: The electronic signature is included in checksum calcula-
tions. Changing the electronic signature will alter the checksum.
The security cell is provided on all GAL20VP8 devices to prevent
unauthorized copying of the array patterns. Once programmed,
the circuitry enabling array is disabled, preventing further program-
ming or verification of the array. The cell can only be erased by re-
programming the device, so the original configuration can never
be examined once this cell is programmed. Signature data is al-
ways available to the user.
GAL20VP8 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pull-ups
instead of the traditional p-channel pull-ups to eliminate any pos-
sibility of SCR induced latching.
During a programming cycle, a clear function performs a bulk erase
of the array and the architecture word. In addition, the electronic
signature word and the security cell are erased. This mode resets
a previously configured device back to its original state, which is
all JEDEC ones.
One of the enhancements of the GAL20VP8 for bus interface logic
implementation is input gysteresis. The threshold of the positive
going edge is 1.5V, while the threshold of the negative going edge
is 1.3V. This provides a typical hysteresis of 200mV between
positive and negative transitions of the inputs.
All eight outputs of the GAL20VP8 are capable of driving 64 mA
loads when driving low and 32 mA loads when driving high. Near
symmetrical high and low output drive capability provides small
skews between high-to-low and low-to-high output transitions.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
Electronic Signature
Signature Cell
Latch-Up Protection
Bulk Erase Mode
Schmitt Trigger Inputs
Bulk Erase Mode
Output Register Preload
14
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL20VP8 device includes circuitry that allows each registered
output to be synchronously set either high or low. Thus, any present
state condition can be forced for test sequencing. If necessary,
approved GAL programmers capable of executing test vectors can
perform output register preload automatically.
The GAL20VP8 devices are designed with TTL level compatible
input buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than
bipolar TTL devices.
GAL20VP8 input buffers have active pull-ups within their input
structure. As a result, unused inputs and I/O's will float to a TTL
"high" (logical "1"). Lattice Semiconductor recommends that all un-
used inputs and tri-stated I/O pins for both devices be connected
to another active input, V
noise immunity and reduce I
In addition to the standard GAL20V8 type configuration, the out-
puts of the GAL20VP8 are individually programmable either as a
standard totempole output or an open-drain output. The totempole
output drives the specified V
drain output drives only the specified V
open-drain output depends on the external loading and pull-up. This
output configuration is controlled by the AC2 fuse. When AC2 cell
is erased (JEDEC "1") the output is configured as a totempole out-
put and when AC2 cell is programmed (JEDEC "0") the output is
configured as an open-drain. The default configuration when the
device is in bulk erased state is totempole configuration. The AC2
fuses associated with each of the outputs is included in all of the
logic diagrams.
Input Buffers
Programmable Open-Drain Outputs
-20
-40
-60
0
0
Specifications GAL20VP8
Typical Input Pull-up Characteristic
1.0
CC
Input Voltage (Volts)
, or GND. Doing this will tend to improve
2.0
CC
OH
and V
for the device.
OL
3.0
levels whereas the open-
OL
. The V
4.0
OH
level on the
5.0