LF398A National Semiconductor, LF398A Datasheet - Page 11

• Manufacturer Part Number: LF398A
• Description: Monolithic Sample-and-Hold Circuits
• Manufacturer: National Semiconductor

Typical Applications
Definition of Terms
Hold Step: The voltage step at the output of the sample and
hold when switching from sample mode to hold mode with a
steady (dc) analog input voltage. Logic swing is 5V.
Acquisition Time: The time required to acquire a new ana-
log input voltage with an output step of 10V. Note that acqui-
sition time is not just the time required for the output to settle,
but also includes the time required for all internal nodes to
settle so that the output assumes the proper value when
switched to the hold mode.
Gain Error: The ratio of output voltage swing to input volt-
age swing in the sample mode expressed as a per cent dif-
ference.
Connection Diagrams
See NS Package Number N08E
Order Number LF398N
Dual-In-Line Package
or LF398AN
Differential Hold
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(Continued)
Order Number LF298M or LF398M
See NS Package Number M14A
DS005692-57
Small-Outline Package
**
11
Adjust for amplitude
Hold Settling Time: The time required for the output to
settle within 1 mV of final value after the “hold” logic com-
mand.
Dynamic Sampling Error: The error introduced into the
held output due to a changing analog input at the time the
hold command is given. Error is expressed in mV with a
given hold capacitor value and input slew rate. Note that this
error term occurs even for long sample times.
Aperture Time: The delay required between “Hold” com-
mand and an input analog transition, so that the transition
does not affect the held output.
Capacitor Hysteresis Compensation
DS005692-15
See NS Package Number H08C
LF398H, LF198AH or LF398AH
Order Number LF198H,
LF198H/883, LF298H,
Metal Can Package
DS005692-56
www.national.com
DS005692-14