P89C668 Philips Semiconductors, P89C668 Datasheet - Page 33

• Manufacturer Part Number: P89C668
• Description: 80C51 8-bit Flash microcontroller family 64KB ISP FLASH with 8KB RAM
• Manufacturer: Philips Semiconductors

11. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS
T
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Capacitive loading on ports 0 and 2 may cause the V
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
5. See Figures 41 through 44 for I
6. This value applies to T
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
9. ALE is tested to V
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
2001 Jul 27
amb
SYM-
BOL
V
V
V
V
V
V
V
V
V
V
I
I
I
I
I
R
C
IL
TL
LI
L2
CC
IL
IL2
IH
IH1
IH2
OL
OL1
OL2
OH
OH1
80C51 8-bit Flash microcontroller family
64KB ISP Flash with 8KB RAM
RST
IO
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
maximum value when V
If I
test conditions.
(except EA is 25 pF).
while an input voltage above 3.0 V will be recognized as a logic 1.
= 0 C to +70 C, 5 V
OL
Active mode:
Idle mode:
Maximum I
Maximum I
Maximum total I
exceeds the test condition, V
Input low voltage
Input low voltage to P1.6/SCL, P1.7/SDA
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Input high voltage, P1.6/SCL, P1.7/SDA
Output low voltage, ports 1, 2, 3
Output low voltage, port 0, ALE, PSEN
Output low voltage, P1.6/SCL, P1.7/SDA
Output high voltage, ports 1, 2, 3
Output high voltage (port 0 in external bus mode),
ALE
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
Input leakage current, P1.6/SCL, P1.7/SDA
Power supply current (see Figure 37):
Internal reset pull-down resistor
Pin capacitance
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see
Programming and erase mode
9
OL
OL
Fi
Figure 44 for conditions)
, PSEN
per port pin:
per 8-bit port:
OH1
OL
I
I
CC(MAX)
CC(MAX)
44 f
, except when ALE is off then V
3
amb
for all outputs:
IN
10% or –40 C to +85 C; 5 V 5%; V
10
is approximately 2 V.
= 0 C to +70 C.
(except EA)
PARAMETER
PARAMETER
= (2.8
= (1.2
CC
diti
test conditions and Figure 37 for I
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
FREQ. + 8.0)mA for all devices, in 6 clock mode; (1.4
FREQ. +1.0)mA in 6 clock mode; (0.6
)
15 mA (*NOTE: This is 85 C specification.)
26 mA
71 mA
8
3
OL
7, 8
11
must be externally limited as follows:
11
OH
OH
6
on ALE and PSEN to momentarily fall below the V
is the voltage specification.
2
SS
C specification, so an input voltage below 1.5 V will be recognized as a logic 0
T
0.45 < V
= 0 V
amb
T
4.5 V < V
33
amb
0 V < V
CC
I
CONDITIONS
0 V < VI < 6 V
I
I
f
= –40 C to +85 C
I
OH
OL
OL
I
osc
V
V
V
OH
V
OL
vs Freq.
V
V
See Note 4
See Note 5
= 0 C to 70 C
CC
CC
CC
CC
IN
IN
= 1.6 mA
= 3.2 mA
= –3.2 mA
TEST
IN
= 20 MHz
= 3.0 mA
= –30 A
= 0.4 V
= 2.0 V
DD
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
CC
< V
FREQ. +1.0)mA in 12 clock mode.
< 5.5 V
< 5.5 V
CC
2
2
– 0.3
OL
OL
0.2V
V
V
FREQ. + 8.0)mA in 12 clock mode.
0.7V
0.7V
CC
CC
s of ALE and ports 1 and 3. The noise is due
can exceed these conditions provided that no
–0.5
–0.5
MIN
–1
40
CC
9
– 0.7
– 0.7
CC
DD
+0.
CC
TYP
LIMITS
20
60
–0.7 specification when the
1
0.2 V
V
V
0.3V
CC
CC
MAX
–650
P89C668
0.45
–75
100
125
225
6.0
0.4
0.4
10
15
CC
10
+0.5
+0.5
DD
Preliminary data
–0.1
UNIT
UNIT
mA
k
pF
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
A