MM1495XD MITSUMI, MM1495XD Datasheet - Page 14

• Manufacturer Part Number: MM1495XD
• Description: I2C BUS Control 5-Input 2-Output AV Switch Monolithic IC
• Manufacturer: MITSUMI

MITSUMI
I
2
S
I
Data are transmitted and received in the units of byte and Acknowledge.
It is transmitted by MSB first from the Start conditions.
[Control registers]
Control registers are data sent from the master for determining the switch conditions.
The data format is set as shown in the following figure.
Out of the Address byte, first 7bit are assigned to the slave address, while the residual 1bit is assigned to the
R/W bit.
Set the R/W bit to 0 when data are used control registers.
As MM1495 slave address, either 90H or 92H can be selected according to the ADR
terminal conditions. When ADR terminal is L, 90H is selected.
The following figure indicates the control contents of control registers and switches.
Each bit of control registers is reset to 0, when power-on.
MM1495 consists of one address byte and three control data bytes (4bytes in total).
All data over the limited length (5th and subsequent bytes) are fully neglected.
For details of the control contents of switches, refer to the separate table.
C BUS
2
C BUS is inter bus system controled by 2 lines (SDA, SCL).
DATA1
DATA2
DATA3
1
No.
0
Slave address
SDA
SCL
0
Address byte
1
b07
b17
b27
O5
S
0
1 2 3
0 0/1 0
Y, C
b06
b16
b26
O4
IN
Y/C select
R/W
1/2
4 5 6 7 8 A
Output port select
A
L
OUT
Y, C
b07 b06 b05 b04 b03 b02 b01 b00
b17 b16 b15 b14 b13 b12 b11 b10
b05
b15
TV R
b25
O3
OUT
OUT
TV L
L
OUT
OUT
DATA1
DATA2
Mute
DATA condition
b04
b14
b24
1 2
O2
1 R
2 R
OUT
OUT
I
2
C BUS Control 5-Input 2-Output AV Switch MM1495X
Mute
1
2
8 A
V
V
b03
b13
b23
OUT
OUT
O1
1
2
P
A
A
b27 b26 b25 b24 b23 b22 b21 b20
b02
b12
b22
Sync sepa select
S:Start Condition
P:Stop Condition
A:Acknowledge
Main V select
Sub V select
DATA3
b01
b11
b21
b00
b10
b20
A P