AT28LV010-20 ATMEL Corporation, AT28LV010-20 Datasheet - Page 3

• Manufacturer Part Number: AT28LV010-20
• Description: 1 Megabit 128K x 8 Low Voltage Paged CMOS E2PROM
• Manufacturer: ATMEL Corporation

Device Operation
READ: The AT28LV010 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention in their system.
WRITE: The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of WE or
CE, whichever occurs last and data is latched on the rising
edge of WE or CE, whichever occurs first. Each succes-
sive byte must be written within 150 s (t
vious byte. If the t
cease accepting data and commence the interal program-
ming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be pre-
sented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
BLC
limit is exceeded the AT28LV010 will
BLC
) of the pre-
TOGGLE BIT: In addition to DATA Polling the AT28LV010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling be-
tween one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inad-
vertent writes may occur during transitions of the host sys-
tem power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV010 in the follow-
ing ways: (a) V
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cy-
cles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: The AT28LV010 in-
corporates the industry standard software data protection
(SDP) function. Unlike standard 5-volt only E
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP com-
mand sequence.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte se-
quence will start the internal timers. No data will be written
to the device. However, for the duration of t
erations will effectively be polling operations.
CC
power-on delay - once V
AT28LV010
CC
WC
has reached
2
, read op-
PROM’s,
2-157