24C01C MicrochipTechnology, 24C01C Datasheet - Page 4

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24C01C

Manufacturer Part Number
24C01C
Description
1K5.0VI2CSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet

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24C01C
2.0
2.1
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
2.2
This input is used to synchronize the data transfer from
and to the device.
2.3
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C01C devices may be connected to the
same bus by using different chip select bit combina-
tions. These inputs must be connected to either V
V
2.4
This pin is utilized for testing purposes only. It may be
tied high, tied low or left floating.
2.5
The 24C01C employs a V
which disables the internal erase/write logic if the V
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
DS21201A-page 4
SS
.
PIN DESCRIPTIONS
SDA Serial Data
SCL Serial Clock
A0, A1, A2
Test
Noise Protection
CC
(typical 10 k
CC
threshold detector circuit
for 100 kHz, 2 k
CC
Preliminary
for
CC
or
3.0
The 24C01C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C01C works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
FUNCTIONAL DESCRIPTION
1997 Microchip Technology Inc.

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