ADG411 Analog Devices, ADG411 Datasheet - Page 6

• Manufacturer Part Number: ADG411
• Description: LC2MOS Precision Quad SPST Switches
• Manufacturer: Analog Devices

ADG411/ADG412/ADG413
110
100
120
100
90
80
70
60
80
60
40
100
100
Figure 7. Off Isolation vs. Frequency
Figure 8. Crosstalk vs. Frequency
1k
1k
FREQUENCY – Hz
FREQUENCY – Hz
10k
10k
100k
100k
V
V
V
V
V
V
DD
SS
L
1M
DD
SS
L
1M
= +5V
= –15V
= +5V
= +15V
= –15V
= +15V
10M
10M
–6–
APPLICATION
Figure 9 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG411/ADG412/
ADG413 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30 V/ s.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711, which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the 10 V input
range. Both the acquisition and settling times are 850 ns.
V
IN
H
.
AD845
+15V
–15V
Figure 9. Fast, Accurate Sample-and-Hold
C
and C
OUT
S
S
follows the input signal V
+15V
SW1
SW2
C
. This compensation network also re-
ADG411
ADG412
ADG413
–15V
+5V
D
D
75
R
C
2200pF
2200pF
C
1000pF
C
C
H
IN
. In the hold
AD711
+15V
–15V
REV. A
V
OUT