GAL26CV12B-20LPI LATTICE [Lattice Semiconductor], GAL26CV12B-20LPI Datasheet - Page 13

• Manufacturer Part Number: GAL26CV12B-20LPI
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the GAL26CV12 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1 s MAX). As a result, the state
on the registered output pins (if they are enabled) will be either high
or low on power-up, depending on the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. Because of the asynchro-
nous nature of system power-up, some conditions must be met to
Power-Up Reset
Input/Output Equivalent Schematics
(Vref Typical = 3.2V)
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
INTERNAL REGISTER
Typical Input
OUTPUT REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
ACTIVE HIGH
Vref
ACTIVE LOW
Q - OUTPUT
C L K
Vcc
V c c
Vcc
Vcc (min.)
13
t
provide a valid power-up reset of the device. First, the V
be monotonic. Second, the clock input must be at static TTL level
as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
pr
Specifications GAL26CV12
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
t
wl
Tri-State
Control
t
Feedback
su
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
(Vref Typical = 3.2V)
PIN
PIN
CC
rise must