ISPLSI8840-60LB432 LATTICE [Lattice Semiconductor], ISPLSI8840-60LB432 Datasheet - Page 14

• Manufacturer Part Number: ISPLSI8840-60LB432
• Manufacturer: LATTICE [Lattice Semiconductor]

Internal Timing Parameters
PARA-
METER
I/O Cell Delay
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GLB / Macrocell Delay
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
idcom
idreg
obp
ibp
iolat
ioco
iosu
ioh
iorst
iosuce
iohce
odreg
odcom
odz
slf
sls
andhs
andlp
1pt
4ptcom 42 Four Product Term Bypass, Combinatorial Macrocell
4ptreg
ptsa
mbp
mlat
mco
msu
mh
mrst
msuce
mhce
ftog
floc
pck
pcken
sck
scken
prst
rdir
23 Input Pad and Input Buffer, Combinatorial Input
24 Input Pad and Input Buffer, Registered Input
25 Output Register/Latch Bypass to Output Buffer
26 Input Register/Latch Bypass to BFM Routing or GRP
27 I/O Cell Latch, Transparent Mode
28 I/O Cell Register/Latch, Clk/Gate to Output
29 I/O Cell Register/Latch, Setup Time
30 I/O Cell Register/Latch, Hold Time
31 I/O Cell Register/Latch, Reset or Set Time
32 I/O Cell Register/Latch, Setup Time for Clk Enable
33 I/O cell Register/Latch, Hold Time for Clk Enable
34 I/O Cell Output Buffer Delay, Registered Output
35 I/O Cell Output Buffer Delay, Combinatorial Output
36 Output Driver Disable Time
37 Slew Rate Adder, Fast Slew Rate
38 Slew Rate Adder, Slow Slew Rate
39 AND Array, High Speed Mode
40 AND Array, Low Power Mode
41 Single Product Term Bypass
43 Four Product Term Bypass, Registered Macrocell
44 Product Term Sharing Array
45 Macrocell Register/Latch Bypass
46 Macrocell Latch, Transparent Mode
47 Macrocell Register/Latch, Clk/Gate to Output
48 Macrocell Register/Latch, Setup Time
49 Macrocell Register/Latch, Hold Time
50 Macrocell Register/Latch, Reset or Set Time
51 Macrocell Register/Latch, Setup Time for Clk Enable
52 Macrocell Register/Latch, Hold Time for Clk Enable
53 Toggle Flip-Flop Feedback
54 Local Feedback to AND Array
55 Single Product Term, Clk
56 Single Product Term, Clk Enable
57 Shared Product Term, Clk
58 Shared Product Term, Clk Enable
59 Single Product Term, Reset or Set Delay
60 Macrocell Register, Direct Input from GRP
#
2
DESCRIPTION
Over Recommended Operating Conditions
14
MIN
0.4
4.1
2.6
0.4
3.8
1.7
1.0
1.0
1.6
1.9
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-110
Specifications ispLSI 8840
MAX
0.1
8.0
0.0
0.2
2.0
1.0
2.3
1.1
1.7
2.0
0.0
5.0
3.6
7.1
3.6
0.2
3.4
3.7
0.0
0.2
0.2
4.0
3.9
1.1
2.5
2.6
2.4
2.4
1.7
1.8
–
–
–
–
–
–
–
–
0.7
4.4
2.7
1.9
0.8
4.5
1.8
0.9
1.5
1.8
MIN
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-90
MAX
0.1
9.4
0.0
0.2
2.4
1.2
2.9
1.3
2.0
2.3
0.0
5.0
4.2
8.4
4.3
0.3
4.4
4.5
0.0
0.3
0.3
5.2
4.7
1.3
3.5
3.1
2.5
2.5
2.0
2.1
–
–
–
–
–
–
–
–
MIN
1.4
6.9
3.8
2.9
1.2
6.1
2.4
1.3
2.3
2.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-60
MAX
13.9
12.6
0.2
0.0
0.4
3.6
2.0
4.4
1.9
3.0
3.5
0.0
7.5
6.4
6.2
0.4
6.1
6.8
0.0
0.9
0.5
7.3
6.8
1.9
5.3
4.6
3.8
3.8
3.0
2.7
–
–
–
–
–
–
–
–
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns