A3P030 ETC2 [List of Unclassifed Manufacturers], A3P030 Datasheet
A3P030
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A3P030 Summary of contents
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... Bank-Selectable I/O Voltages— Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except A3P030), and LVCMOS 2 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS (A3P250 and above) • I/O Registers on Input, Output, and Enable Paths • ...
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... ProASIC3 Flash Family FPGAs 1 I/Os Per Package ProASIC3 Devices A3P030 A3P060 ARM-Enabled ProASIC3 Devices Package QN132 81 80 VQ100 77 71 TQ144 – 91 PQ208 – – FG144 – 96 FG256 – – FG484 – – Notes: 1. Each used differential I/O pair reduces the number of single-ended I/Os available by two. ...
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... FG Package Type Speed Grade F = 20% Slower than Standard* Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number ProASIC3 Devices A3P030 = 30,000 System Gates A3P060 = 60,000 System Gates A3P125 = 125,000 System Gates A3P250 = 250,000 System Gates A3P400 = 400,000 System Gates ...
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... ProASIC3 Flash Family FPGAs Temperature Grade Offerings A3P030 A3P060 Package QN132 C, I VQ100 C, I TQ144 – PQ208 – FG144 – FG256 – FG484 – Notes: 1. The M7A3P250 device does not support FG256 or QN132 packages Commercial temperature range: 0°C to 70° Industrial temperature range: – ...
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... FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P030 device has no PLL or RAM support. ProASIC3 devices have million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 288 user I/Os. ...
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... ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. 1. The A3P030 does not support PLL or SRAM. 6 ProASIC3 devices consumption to further maximize power savings. ...
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... ISP AES Decryption* Note: *Not supported by AGL030 Figure 1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, and A3P125) ISP AES Decryption Figure 2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) Bank 0 User Nonvolatile Charge Pumps ...
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... IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on- chip AES decryption can be used selectively to securely load data over public networks (except in the A3P030 device security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG ...
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... Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P030 does not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. ...
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ProASIC3 Flash Family FPGAs Related Documents Application Notes ProASIC3/E I/O Usage Guide http://www.actel.com/documents/PA3_E_IO_AN.pdf In-System Programming (ISP) in ProASIC3/E Using FlashPro3 http://www.actel.com/documents/PA3_E_ISP_AN.pdf ProASIC3/E FlashROM http://www.actel.com/documents/PA3_E_FROM_AN.pdf ProASIC3/E Security http://www.actel.com/documents/PA3_E_Security_AN.pdf ProASIC3/E SRAM/FIFO Blocks http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf Programming a ProASIC3/E Using a Microprocessor http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf UJTAG Applications ...
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