PEX8664-16U8DBBRDK PLX [PLX Technology], PEX8664-16U8DBBRDK Datasheet - Page 4

• Manufacturer Part Number: PEX8664-16U8DBBRDK
• Description: PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
• Manufacturer: PLX [PLX Technology]

server design where, in a quad or multi processor
system, users can assign endpoints/slots to CPU cores to
distribute the system load. The packets directed to
different CPU cores will go to different (user assigned)
PEX 8664 upstream ports, allowing better queuing and
load balancing capability for higher performance.
Embedded or Communications Systems
The PEX 8664’s 64 lanes can come in handy for
embedded or communications applications requiring
heavy processing and/or connectivity to multiple
endpoints. Figure 7a shows an embedded system where
the PEX 8664 is being used to fan-out to eight endpoints
using x8 and x16 links. Figure 7b shows a
communications system where the PEX 8664 is using
x16 downstream links to fan out to three CPUs which
have been configured as endpoints. These CPUs will run
as endpoints, conducting different processing tasks while
the host CPU (connected to the PEX 8664 via a x16
upstream link) manages them.
Host Failover
The PEX 8664 can also be utilized in applications where
host failover is required. In the application shown in
Figure 8, two hosts may be active simultaneously and
controlling their own domains while exchange status
© PLX Technology, www.plxtech.com
Figure 6. Host Centric Dual Upstream
Figure 7a. Embedded System
Figure 7a. Embedded System
Figure 7a. Embedded System
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Endpoint
Endpoint
Endpoint
Endpoint
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Endpoint
Endpoint
Endpoint
Endpoint
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
Set
Set
Set
Set
Set
Set
Set
Set
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
x16
x16
x16
x16
x4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
x16
PCIe Gen1 or PCIe Gen2 slots
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
x8s
x8s
x8s
x8s
x8s
Chipset
Chipset
Chipset
Chipset
CPU
CPU
CPU
CPU
PEX 8664
PEX 8664
PEX 8664
PEX 8664
CPU
CPU
CPU
CPU
x8
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Figure 7b. Comms System
Figure 7b. Comms System
Figure 7b. Comms System
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
x8
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
PEX 8664
Chip
Chip
Chip
Chip
Chip
Chip
Chip
Chip
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
Memory
Memory
Memory
Memory
Set
Set
Set
Set
Set
Set
Set
Set
PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports
x16
x16
x16
x16
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
x4s
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
x16s
x16s
x16s
x16s
Page 4 of 4
information through doorbell registers or I
The devices can be programmed to trigger fail-over if
the heartbeat information is not provided. In the event of
a failure, the surviving device will reset the endpoints
connected to the failing CPU and enumerate them in its
own domain without impacting the operation of
endpoints already in its domain.
N+1 Fail-Over in Storage Systems
The PEX 8664’s Multi-Host feature can also be used to
develop storage array clusters where each host manages
a set of storage devices independent of others. Users can
designate one of the hosts as the failover-host for all the
other hosts while actively managing its own endpoints.
The failover-host will communicate with other hosts for
status/heartbeat information and execute a failover event
if/when it gets triggered (see Figure 9).
8 Disk Chassis
8 Disk Chassis
x4
x4
FC
FC
FC
FC
x8
Figure 8. Host Fail-Over
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
x4
Figure 9. N+1 Failover
Chipset
Chipset
Chipset
Chipset
PEX 8664
PEX 8664
PEX 8664
PEX 8664
x4
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
FC
FC
FC
FC
8 Disk Chassis
8 Disk Chassis
x4
x4
x4
x4
x4
x4
FC
FC
FC
FC
PEX 8664
PEX 8664
PEX 8664
PEX 8664
CPU
CPU
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
PEX 8612
x4 & x8
8 Disk Chassis
8 Disk Chassis
x8s
FC
FC
FC
FC
x4
x4
FC
FC
FC
FC
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
x4
x4
CPU
CPU
x8
x8
8 Disk Chassis
8 Disk Chassis
Chipset
Chipset
Chipset
Chipset
FC
FC
FC
FC
CPU
CPU
CPU
CPU
PEX 8664
PEX 8664
PEX 8664
PEX 8664
x4
x4
FC
FC
FC
FC
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
PEX 8616
x4
x4
CPU
CPU
CPU
CPU
CPU
CPU
x8
x8
5/14/2009, Version 1.1
FC
FC
FC
FC
x8
x4
x4
2
C interface.