ISPPAC30-01SI LATTICE [Lattice Semiconductor], ISPPAC30-01SI Datasheet - Page 29

• Manufacturer Part Number: ISPPAC30-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
(see timing specifications). As with the programming instructions above, calibration does not begin until entry of the
Run-Test/Idle state. The completion of the calibration is not dependent, however, on any further TAP control. This
means the state of the TAP can be returned immediately to the Test-Logic-Reset state. The only consideration
would be to not clock the TAP during critical analog operations. The first several milliseconds of the calibration rou-
tine are consumed waiting for configurations to settle, though, leaving more than enough time to clock the TAP back
to the Test-Logic-Reset state. The bit code for this instruction is shown in Table 6.
The POWERDN (power down command) and POWERUP (power up command) are unique instructions specified
by Lattice for the ispPAC30 to command the normal and low-power or shut-down states of the device. As with other
instructions above, these instructions do not begin until entry of the Run-Test/Idle state. Timing for coming out of
power-down mode as well as supply current used in this mode are specified in the spec tables of this data sheet.
All analog is shut down and outputs are in a high-impedance mode during power-down state. Device digital cir-
cuitry is not shut down and consumes no power unless it is clocked, and even then only a minimal amount. The bit
code for these instructions is shown in Table 6.
The last unique Lattice instructions are ERASECFG (erase or clear CFG), ERASEUES (erase or clear the UES)
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and CFGBE (erase or clear all user memory). These instructions set all the bits of their respective E
storage cells
to all zeros. Operation of the device is not interrupted during any of these instructions. The CFGBE is used to return
all user controlled bits to a zero state at the same time (CFG, UES and ESF) and is the only way to erase the ESF
bit. The condition after a CFGBE instruction is the default condition of parts shipped from the factory. The same
programming timing constraints apply to these instructions as for the PROG programming instructions listed above.
2
The bit code for these instructions are shown in Table 6. Important Note: Programming E
configuration memory
can only program ones into a device, not zeros. Erase instructions are required to change all bits to zero first. The
2
2
normal sequence to re-program E
configuration memory is first erase either the CFG or UES E
cells and then
program them with the desired bit sequence and PRG instructions.
Once again, the JTAG PROG, LATCHCFG, ERASE, POWERUP, POWERDN, RELOADCFG and ENCAL instruc-
tions do not execute until entry of the Run-Test/Idle state. All other instructions are executed in the Update-IR state,
allowing shifts and other operations to occur without having to leave the inner loop of the JTAG controller.
It is recommended that when all serial interface operations are completed, the TAP controller be reset and left in
the Test-Logic-Reset state (the power-up default) and the TCK and TMS inputs idled. This will insure the best ana-
log performance possible by minimizing the effects of digital logic “feed-through.”
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