ISPPAC10-01SI LATTICE [Lattice Semiconductor], ISPPAC10-01SI Datasheet - Page 5

• Manufacturer Part Number: ISPPAC10-01SI
• Description: In-System Programmable Analog Circuit
• Manufacturer: LATTICE [Lattice Semiconductor]

Connection Notes
1. All inputs and outputs are labeled with plus (+) and
2. All analog output pins are “hard-wired” to internal
3. When the signal input is single-ended, the other half of
Pin Descriptions
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
minus (-) signs. Polarity is labeled for reference and
can be selected externally by reversing pin connec-
tions or internally under user programmable control.
output devices and should be left open if not used.
Outputs of uncommitted PACblocks are forced to
VREF
reference output buffers. V
be tied together as unnecessary power will be dissi-
pated.
the unused differential input must be connected to a
DC common-mode reference (usually VREF
Symbol
OUT2+
OUT2-
IN2+
IN2-
TDI
TRST
VS
TDO
TCK
TMS
IN4-
IN4+
OUT4-
OUT4+
OUT3+
OUT3-
IN3+
IN3-
CMV
CAL
GND
VREF
TEST
TEST
IN1-
IN1+
OUT1-
OUT1+
OUT
IN
OUT
(2.5V) and can be used as low impedance
Output 2(+)
Output 2(-)
Input 2(+)
Input 2(-)
Test Data In
Test Reset
Supply Voltage
Test Data Out
Test Clock
Test Mode Select
Input 4(-)
Input 4(+)
Output 4(-)
Output 4(+)
Output 3(+)
Output 3(-)
Input 3(+)
Input 3(-)
Input for V
Auto-Calibrate
Ground
Common-Mode Reference
Test Pin
Test Pin
Input 1(-)
Input 1(+)
Output 1(-)
Output 1(+)
Name
CM
Reference
OUT+
and V
Differential output pin, V
where differential V
Differential output pin, V
Differential input pin, V
Differential input pin, V
Serial interface logic input pin. Input data valid on rising edge of TCK.
Serial interface logic reset pin (input). Asynchronously resets logic controller. Active low.
Reset is equivalent of power-on default.
Analog supply voltage pin (5V nominal).
Should be bypassed to GND with 1 F and .01 F capacitors.
Serial interface logic output pin. Input data valid on falling edge of TCK.
Serial interface logic clock pin (input). Best analog performance when TCK is idle.
Differential output pin, V
Differential output pin, V
Input pin for optional (external) analog Common-Mode Voltage (V
(+2.5V) for any so programmed PACblock as its common-mode output voltage value.
Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND
with a 0.1 F capacitor.
Manufacturing test pin. Connect to GND for proper circuit operation.
Manufacturing test pin. Connect to GND for proper circuit operation.
Differential output pin, V
Serial interface logic mode select pin (input).
Differential input pin, V
Differential input pin, V
Differential output pin, V
Differential output pin, V
Differential input pin, V
Differential input pin, V
Digital input pin. Commands an auto-calibration sequence on a rising edge.
Ground pin. Should normally be connected to analog ground plane.
Differential input pin, V
Differential input pin, V
Differential output pin, V
OUT-
OUT
should not
, 2.5V).
OUT
5
Pin Configuration
IN
IN
IN
IN
IN
IN
IN
IN
= V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
+
-
-
+
+
-
-
+
. (Minus component of differential V
. (Plus V
OUT
+
-
-
+
+
-
-
+
. (Minus component, where differential V
. (Plus complement of V
+
- V
IN
OUT
Specifications ispPAC10
, where differential V
Description
VS (5V)
OUT2+
OUT2–
OUT4–
OUT4+
-
TRST
).
IN2+
IN2–
TDO
TMS
IN4+
IN4–
TCK
TDI
Top View
28-Pin
1
OUT
IN
with respect to VREF
= V
OUT1+
OUT1–
IN1+
IN1–
TEST (tie to GND)
TEST (tie to GND)
VREFout
GND (0V)
CAL
CMVin
IN3–
IN3+
OUT3–
OUT3+
IN
IN
, where V
+
CM
- V
). Replaces VREF
OUT
IN
-
).
IN
= V
= V
OUT
IN
OUT
+
+
- V
- V
,
IN
OUT
-
OUT
).
-
).