XR16M2550IL32 EXAR [Exar Corporation], XR16M2550IL32 Datasheet
XR16M2550IL32
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XR16M2550IL32 Summary of contents
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HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO MAY 2007 GENERAL DESCRIPTION 1 The XR16M2550 (M2550 high performance dual universal asynchronous receiver and transmitter (UART) with 16 bytes TX and RX FIFOs. The device operates from 1.62 to ...
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... IN UT SSIGNMENT RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# NC RXB RXA TXA TXB CSA# CSB# ORDERING INFORMATION ART UMBER XR16M2550IL32 32-Pin QFN XR16M2550IM48 48-Lead TQFP XR16M2550 6 48-pin TQFP XR16M2550 ...
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REV. 1.0.2 PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP N AME DATA BUS INTERFACE ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA CTSA# 25 ...
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REV. 1.0.2 Pin Description 32-QFN 48-TQFP N AME RTSB CTSB DTRB DSRB CDB RIB OP2B ANCILLARY SIGNALS XTAL1 10 13 ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16M2550 (M2550) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the ...
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REV. 1.0.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The M2550 data interface supports the Intel compatible types ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO registers, but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1. CSA 2.5 Channel A and B Internal ...
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REV. 1.0.2 2.7 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through 22. ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected ...
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REV. 1.0 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.10 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data ...
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REV. 1.0 IGURE RANSMITTER PERATION IN Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg.) Auto Software Flow Control 16X Clock (DLD[5:4]) 2.11 Receiver The receiver ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO IGURE ECEIVER PERATION IN NON ...
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REV. 1.0.2 2.12 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 ...
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REV. 1.0.2 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M2550 will halt transmission (TX) as soon ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.17 Infrared Mode The M2550 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends ...
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REV. 1.0.2 2.18 Sleep Mode with Auto Wake-Up The M2550 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.19 Internal Loopback The M2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 1.0.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M2550 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO . T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable XON1 RD/WR Bit ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M2550 in the FIFO polled mode of ...
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REV. 1.0.2 IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 1.0.2 FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers (the receive shift register is ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select ...
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REV. 1.0.2 LCR B -5 LCR LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO MCR[3]: OP2# Output / INT Output Enable This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general ...
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REV. 1.0.2 LSR[3]: Receive Data Framing Error Tag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time ...
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REV. 1.0.2 4.13 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). 4.14 ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data ...
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REV. 1.0.2 T 15: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (48-TQFP) Thermal Resistance (32-QFN) ...
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REV. 1.0.2 AC ELECTRICAL CHARACTERISTICS o Unless otherwise noted: TA=- YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock Time Period ECLK T Address Setup Time AS T Address Hold Time AH T ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 13 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# ...
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REV. 1.0 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING A0-A2 Valid Address T AS ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 17 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in ...
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REV. 1.0.2 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL HIGH PERFORMANCE LOW ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 mm) Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS ...
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REV. 1.0.2 REVISION HISTORY D R ATE EVISION March 2006 P1.0.0 Preliminary Datasheet. July 2006 P1.0.1 Updated ordering information for 48-TQFP package. January 2007 1.0.0 Final Datasheet. Updated AC Electrical Characteristics. May 2007 1.0.1 Added "GND Center Pad" to pin ...
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XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M2550 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ...
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REV. 1.0.2 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ FIFO T ABLE RANSMIT AND ...