XR16L580_07 EXAR [Exar Corporation], XR16L580_07 Datasheet - Page 9

• Manufacturer Part Number: XR16L580_07
• Description: SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
• Manufacturer: EXAR [Exar Corporation]

REV. 1.4.1
The L580 can accept up to 5V inputs when operating at 3.3V or 2.5V. But note that if the L580 is operating at
2.5V, its V
is operating at 5V. Note that the XTAL1 pin is not 5V tolerant when external clock supply is used.
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see
reset function in the device.
The XR16L580 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to
indicate XR16L580 and reading the content of DLL will provide the revision of the part; for example, a reading
of 0x01 means revision A.
The L580 has a set of enhanced registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard 16C550. These registers
function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control
register (FCR), receive line status and control registers, (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad
register (SPR).
Beyond the general 16C550 features and capabilities, the L580 offers enhanced feature registers (EFR, Xon1,
Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in
REGISTERS” on page 22
The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the
RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the
XR16L580. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’.
The interrupt output changes according to the operating mode and enhanced features setup.
Table 2
modes. Also see Figures
2.2
2.3
2.4
2.5
2.6
2.7
(16/68# = 1)
(16/68# = 0)
IRQ# Pin
INT Pin
5-Volt Tolerant Inputs
Device Hardware Reset
Device Identification and Revision
Internal Registers
DMA Mode
INT (IRQ#) Output
below summarize the operating behavior for the transmitter and receiver in the Intel and Motorola
OH
may not be high enough to meet the requirements of the V
0 = one byte in THR
1 = THR empty
1 = one byte in THR
0 = THR empty
FCR B
Table 11
21
.
IT
T
through
ABLE
-0 = 0 (FIFO D
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
). An active pulse of longer than 40 ns duration will be required to activate the
1: INT (IRQ#) P
24
.
ISABLED
)
IN
O
9
PERATION FOR
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
1 = FIFO above trigger level
0 = FIFO below trigger level or FIFO empty
T
FCR B
RANSMITTER
IH
of a CPU or a serial transceiver that
“Section 3.0, UART INTERNAL
IT
-0 = 1 (FIFO E
NABLED
XR16L580
)
Table 1
and